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| | Method of forming gate spacer to control the base width of a lateral bipolar junction transistor using SOI technology - ... (Site not responding. Last check: 2007-10-15) |
 | | The method of claim 1, wherein said polysilicon layer is patterned using reactive ion etching using a chlorine based etch chemistry, resulting in said polysilicon gate structure with a width between about 0.1 to 1.0 micrometers. |
 | | The method of claim 1, wherein said second insulator layer is silicon oxide, deposited using either LPCVD or PECVD processing, at a temperature between about 600° to 800° C., to a thickness between about 800 to 2500 Angstroms. |
 | | The method of claim 10, wherein said polysilicon layer is patterned via reactive ion etching, using a chlorine etch chemistry, to form said polysilicon gate structure with a width between about 0.1 to 1.0 micrometers. |
| www.patentstorm.us /patents/5567631.html (3212 words) |
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