| | Delay line separator for data bus - Patent 5412697 |
 | | The delay line separator of claim 4, wherein each of said delay means of said delay line provides a delay of approximately 10 nanoseconds, said pulses of said pulse signal have a width of approximately 10 nanoseconds, and said pulse stretchor increases said pulse width to approximately 20 nanoseconds. |
 | | To decode the 4B5B packet to extract the transmitted data, a clock signal encoded within the data packet must first be extracted. |
 | | These and other objects of the invention are achieved by a delay line separator for extracting a clock signal from a combined clock/data signal received along a serial data line with the combined signal including pulses bounded by signal level transitions of first and second types, such as rising and falling edges. |
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