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Topic: 8259A

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	[No title]
		The 8259A has a priority mechanism, so that lower priority interrupt sources do not interrupt the CPU while it is servicing a higher priority interrupt -- but a higher priority interrupt will be passed on to the processor.
		The 8259A interrupt output is known as INT, which is connected to the CPU (wait for it) INTR, or to another 8259A's IRQ.
		One 8259A (known as #1, I/O address #020..#03F) is the "Master" and the other is a "Slave" (known as #2, I/O address #0A0..#0BF).
	www.hackcanada.com /blackcrawl/elctrnic/i8259tut.txt (1384 words)

	Interrupts
		INTA is an output of the microprocessor to signal the external decoder to place the interrupt number on data bus connections D7-D0.
		The 8259A automatically determines which interrupt was active and re-enables it and lower priority interrupts.
		The 8259A is decoded at 48H and 49H.
	www.csee.umbc.edu /~plusquel/310/slides/8086_interrupts.html (875 words)

	Programable interrupt controller - Patent 5261107
		Depending on which type of microprocessor the 8259A is programmed for, in response to an interrupt request input, the 8259A will interrupt the CPU and provide either a subroutine call instruction followed by an interrupt service routine address or an eight bit interrupt vector over the system bus to the CPU.
		The 8259A may be configured to detected interrupt requests on its interrupt request inputs as either low-to-high voltage transitions or as high voltage levels.
		While the 8259A uses this single bit to program all interrupt request inputs to be either edge-sensitive or level-sensitive, the present preferred embodiment uses this same bit to select either edge-sensitivity for all interrupt request inputs or selectability on a per interrupt basis through the use of the bits in the ICW5 register 108.
	www.freepatentsonline.com /5261107.html (9754 words)

	i386 Interupt Handling (Site not responding. Last check: 2007-10-13)
		The 8259A is had 8 inputs, 1 interupt line, and a way for the proccessor to query it.
		When that IRQ fires the 8259A remembers which line it came in on and reaises it's interupt line which is connected to the proccessor.
		When the 8259A is in Manual EOI mode (ICW4[1]==0) it will wait for an EOI (End Of Interrput) acknowlegment to be written to it before it will send any more.
	www.acm.uiuc.edu /sigops/roll_your_own/i386/irq.html (431 words)

	Intel 8259 - Wikipedia, the free encyclopedia
		The Intel 8259 is a family of Programmable Interrupt Controllers (PICs) designed and developed for use with the Intel 8085 and Intel 8086 8-bit and 16-bit microprocessors.
		The 8259 acts as a multiplexer, combining multiple interrupt input sources into a single interrupt output to interrupt a single device.
		It is believed that the NEC Corporation created the 8259A, and the 8259B may be nothing more than a mnemonic for the second 8259A introduced in the PC/AT.
	en.wikipedia.org /wiki/8259A (1219 words)

	Art of Assembly: Chaper Seventeen-3
		These devices connect to an Intel 8259A programmable interrupt controller (PIC) that prioritizes the interrupts and interfaces with the 80x86 CPU.
		The 8259A chip adds considerable complexity to the software that processes interrupts, so it makes perfect sense to discuss the PIC first, before trying to describe how the interrupt service routines have to deal with it.
		The 8259A (8259[6] or PIC, hereafter) programmable interrupt controller chip accepts interrupts from up to eight different devices.
	webster.cs.ucr.edu /AoA/DOS/ch17/CH17-3.html (2537 words)

	CMPE120 Lecture Note: Flow of Control (Site not responding. Last check: 2007-10-13)
		The 8259A is had 8 inputs (IR0-IR7), 1 INT and 1 INTA which are connected to INTR and INTA of CPU.
		The 8259A does not drive the Data Bus during this cycle.
		During this pulse, the 8259A releases an 8-bit pointer onto the Data Bus where it is read by the CPU.
	www.engr.sjsu.edu /cfu/cmpe120/Flow_of_Control/3.html (193 words)

	Computer Science 314 - 8259 Interrupt Controller
		A single 8259A PIC can handle 8 separate interrupts and multiple PICs can be cascaded to handle up to 64 interrupts.
		Communication with the 8259A is facilitated by sending various commands over the bus to the two I/O ports (port A and port B) of the controller.
		The 8259A PIC is initialized by sending a sequence of initialization control words (ICWs) to the controller.
	www.cs.sun.ac.za /~lraitt/doc_8259.html (1612 words)

	General PC Troubleshooting Tips (Site not responding. Last check: 2007-10-13)
		Nowadays, this is integrated into a single chip but the functionality is essentially the same as if it was referencing two 8259A controllers.
		A first 8259A controller will run from IRQ 0 to IRQ 7.
		The second 8259A controller will be cascaded from the IRQ2 connection from the first controller into IRQ 9 of the second controller.
	resource.intel.com /telecom/support/tnotes/gentnote/dl_hard/tn169.htm (1755 words)

	Programmable interrupt controller - Patent 5101497
		To accommodate this, interrupt controllers like the 8259A from Intel Corporation have been designed to allow the user to designate upon initialization of the system which interrupt convention is to be sensed.
		2 is a schematic illustration of the simplified logic circuit of the 8259A relating to interrupt recognition.
		During initialization the 8259A interrupt controller in response to user designation issues one of two command words which set the controller to recognize edge sensed interrupts or disables the edge sense logic to permit interrupts to be recognized by the controller upon receipt of a level high interrupt request (FIG.
	www.freepatentsonline.com /5101497.html (4517 words)

	LKML: Emmanuel Fleury: spurious 8259A interrupt
		Hi, I noticed today that I had several "spurious 8259A interrupt": Dec 20 15:02:45 hermes vmunix: spurious 8259<3>[drm:radeon_cp_init] ERROR radeon_cp_init called without lock held...
		Dec 20 16:54:17 hermes vmunix: spurious 8259A interrupt: IRQ7.
		Mar 8 03:11:24 hermes vmunix: spurious 8259A interrupt: I<7>orinoco_lock() called with hw_unavailable (dev=d5a80000) After some Googling, I found out this: http://test.linuxfromscratch.org/faq/#spurious-8259A-interrupt So, I know it is no harm.
	lkml.org /lkml/2004/3/16/227 (229 words)

	[rlug] Re: spurious 8259A interrupt: IRQ7
		[rlug] Re: spurious 8259A interrupt: IRQ7 mihai Badici
		[rlug] Re: spurious 8259A interrupt: IRQ7 Razvan Cosma
		[rlug] Re: spurious 8259A interrupt: IRQ7 Silviu Vulcan
	www.mail-archive.com /rlug@lug.ro/msg28168.html (376 words)

	Dark Realms - Interrupts and Handlers (Part 1 - Version 1.20)
		The 8259A PIC acts like a bridge between the processor and the interrupt-requesting components, that is, the interrupt requests are first transferred to the 8259A PIC, which in turn drives the interrupt line to the processor.
		For example, as the name indicates the 8259A programmable interrupt controller can be programmed under several different modes and for a defined operation it needs to be initialized first.
		Another characteristic of the 8259A PIC is its cascading capability, that is, the possibility to interconnect one master and up to eight slave PIC's in an application.
	pages.cpsc.ucalgary.ca /~walpole/325/INTHANDLERS1/inthandlers1.html (7400 words)

	Intel 386EX Microprocessor
		These modes are similar to the industry standard 8259A architecture.
		The 8259A module can be programmed to recognize either an active-high level or a positive transition on the interrupt request lines.
		Up to four external 8259A units can be cascaded to the master through connections to the INT3:0 pins.
	www.ssv-embedded.de /ssv/pc104/p8.htm (1799 words)

	Programming Interrupts for DOS-Based Data Acquisition on 80x86-Based Computers- Developer Zone - National Instruments
		Hardware interrupts are sent to the processor through an Intel 8259A programmable interrupt controller, which provides the system with eight prioritized hardware interrupts.
		When the 8259A receives an interrupt request, typically from a peripheral device, the controller drives high its output (INT), which is connected to the processor's interrupt input pin (INTR).
		The INTR pin is used by the processor to signal the occurrence of a maskable interrupt.
	zone.ni.com /devzone/cda/tut/p/id/2874 (4995 words)

	Spurious 8259A interrupt: IRQ7 (Site not responding. Last check: 2007-10-13)
		Re: 'spurious 8259A interrupt: IRQ7', to which Alan Cox replies it's IO-APIC problem.
		The spurious 8259A interrupt is most likely an AMD-only problem.
		I just bought a new Dell 600SC, installed stock RedHat 9 on it, ran up2date which updated everything to current as of Mar 07, 2004 (including kernel 2.4.20-30.9) and I am seeing this same message on the console: spurious 8259A interrupt: IRQ 7.
	jmz.iki.fi /blog.php/en/article/1057989236 (1328 words)

	[No title] (Site not responding. Last check: 2007-10-13)
		To follow the discussion below, you should get hold of the datasheet for the Intel 8259A Programmable Interrupt Controller (which can be found at http://bochs.sourceforge.net/techspec/).
		In P3 we use the Intel 8259A Programmable Interrupt Controller (PIC) to generate interrupts that implement preemption.
		Old PC's used to have two of these controllers, but on modern PC's these (and other legacy chips) are integrated into the chipset.
	www.ifi.uio.no /~inf3150/tfaq3.html (453 words)

	[comp.unix.bsd] NetBSD, FreeBSD, and OpenBSD FAQ (Part 4 of 10)
		In the latter case the corresponding in-service (IS) bit of the 8259A is set (effectively blocking interrupts of lower priority).
		The 8259A receives an unmasked interrupt request (IRQn), and, in case an interrupt is being served and has higher priority than IRQn, the IS bit of the 8259A is reset by an end of interrupt (EOI) command.
		It is preserved by the associated edge sense latch of the 8259A, and will be acted on after the IM bit has been reset again.
	www.cs.uu.nl /wais/html/na-dir/386bsd-faq/part4.html (7759 words)

	Microprocessor Interfacing Notes and Other Information (Site not responding. Last check: 2007-10-13)
		The priority resolver section of the 8259A determines the highest priority of the bits set within the IRR.
		The A0 input, is used in conjunction with the RD and WR lines to determine which of the command and status registers with the controller will be accessed.
		MAIN_CODE ENDS The key to using the 8259A PIC is the correct initialisation sequence required for the desired operating mode.
	www.eng.um.edu.mt /~ppdebo/mif.htm (2892 words)

	Power Developer - Forums
		The problem is that the 8259A is designed for x86 and expects a certain behaviour of the processor (interrupt acknowledge sequence).
		The via southbridge and its embedded 8259A interrupt controller is interfaced to that pin, and you will then get a powerpc external interrupt each time an interrupt is send to the 8259A.
		The interrupt vector should then easily enough investigate what happened on the 8259A for which you have the docs and act acordyingly.
	www.powerdeveloper.org /forums/viewtopic.php?t=302 (1457 words)

	J!NX Forums - IRQ & PIC
		For your questions though: each 8259A chip has 8 IRQ "lines", which are just pins on the chip.
		These were connected to IRQ lines on the (obsolete) ISA bus for x86's.
		I don't think the 8259A is related to DMA, however I can't find the specification sheet on intels site.
	www.jinxhackwear.com /forum/topic.asp?TOPIC_ID=56229 (1648 words)

	8259 Programmable Interrupt Controller (Site not responding. Last check: 2007-10-13)
		The 8259 PIC is functionally based on the Intel 8259A.
		Eight interrupt requests are prioritized for a processor.
		To minimize size and maximize performance, Innocor's PIC selects only the functionality of the Intel 8259A.
	www.altera.com /products/ip/iup/peripherals/m-inn-8259.html (88 words)

	Art of Assembly: Chapter Twenty-Two-2
		One thing this call does not do that you should is patch the break and critical error exception vectors (int 23h and int 24h) to handle any program aborts that come along.
		It restores the original value of the 8259A interrupt enable register, it restores the int 0Ch interrupt vector, and it masks interrupts on the 8250 SCC.
		Doing so would patch the int 0Ch vector with garbage and, likewise, restore the 8259A interrupt enable register with a garbage value.
	maven.smith.edu /~thiebaut/ArtOfAssembly/CH22/CH22-2.html (4768 words)

	Re: spurious 8259A interrupt: IRQ7
		Oct 26 12:56:47 staff kernel: spurious 8259A interrupt: IRQ7.
		A device with part number 8259A, which is a programmable interrrupt controller use
		Oct 26 10:51:42 staff kernel: spurious 8259A interrupt: IRQ7.
	www.redhat.com /archives/enigma-list/2002-October/msg00586.html (443 words)

	PRB: Single Stepping IN to 8259A Controller Gives Wrong Result (Site not responding. Last check: 2007-10-13)
		CodeView disables all interrupts at the interrupt controller when single-stepping an instruction.
		If you single-step an IN instruction that accesses an 8259A interrupt controller, the value returned will be 0xFF and not the true value you would expect.
		This is a restriction imposed by the 8086 chip, which forces CodeView to disable interrupts when single-stepping.
	support.microsoft.com /kb/12401 (219 words)

	./arch/i386/kernel/i8259.c
		The 8259A is a fragile beast, it pretty * much _has_ to be done exactly like this (mask it * first, _then_ send the EOI, and the order of EOI * to the two 8259s is important!
		We do not want * to overdo spurious IRQ handling - it's usually a sign * of hardware problems, so we only do the checks we can * do without slowing down good hardware unnecesserily.
		if (!(spurious_irq_mask & irqmask)) { printk("spurious 8259A interrupt: IRQ%d.\n", irq); spurious_irq_mask = irqmask; } irq_err_count++; /* * Theoretically we do not have to handle this IRQ, * but in Linux this does not cause problems and is * simpler for us.
	www.verifysoft.com /2001/i8259.c.html (1185 words)

	Spurious 8259A interrupt: IRQ7 (Site not responding. Last check: 2007-10-13)
		I found this in the kernel mail archives.
		Hope it helps :) http://mailman.real-time.com/pipermail/linux-kernel/2000-December/011688.html./andy ----- Original Message ----- From: "Kevin Krumwiede" To: Sent: Friday, July 13, 2001 8:44 PM Subject: Spurious 8259A interrupt: IRQ7 > At random intervals, the message 'Spurious 8259A interrupt: IRQ7' appears in > the midst of other console output.
		I gather it's caused by an interrupt for > which there is no defined handler, and the default handler is what spits out > this message.
	www.linuxfromscratch.org /pipermail/lfs-dev/2001-July/016470.html (160 words)

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