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	8B/10B encoding - Wikipedia, the free encyclopedia
		They are often used to indicate end-of-frame, link idle, skip and similar link-level conditions.
		Because 8B/10B encoding uses 10-bit symbols to encode 8-bit words, each of the 256 possible 8-bit words can be encoded in two different ways, one the bit-wise inverse of the other.
		Among the areas in which 8B/10B encoding finds application are HyperTransport, PCI Express, IEEE 1394b, Serial ATA, Fibre Channel, SSA, Gigabit Ethernet, InfiniBand, XAUI, Serial RapidIO and audio storage devices such as the Digital Audio Tape and Digital Compact Cassette (DCC).
	en.wikipedia.org /wiki/8B10B (450 words)

	Algorithm Analysis Package helps debug serial bus design., Agilent Technologies, In
		8B/10B is an algorithm that encodes data for transmission over high-speed serial buses, including PCI Express, Serial ATA and Fibre Channel.
		Using the SDA package, engineers now can superimpose the 8B/10B codes on their waveforms, search waveforms for a given series of codes, or trigger the oscilloscope until the specified series of codes are found.
		The 8B/10B decode capabilities then can be used to see which activity led to the failure.
	news.thomasnet.com /fullstory/451436/2585 (1121 words)

	Cisco ONS 15454 DWDM Troubleshooting Guide, Release 6.0 - Chapter 5, Performance Monitoring [Cisco ONS 15400 ... (Site not responding. Last check: 2007-10-25)
		For ONS 15454 optics and 8b10b definitions, see the "Optics and 8b10b PM Parameter Definitions" section.
		8b10b takes 8 bits of data and sends it as 10 bits, which allows control information to be sent along with the data.
		Errors is a count of 10b errors received by the serial or deserializer (serdes 8b/10b).
	www.cisco.com /en/US/products/hw/optical/ps2006/prod_troubleshooting_guide_chapter09186a00805496fc.html (5943 words)

	8B10B Encoder/Decoder MegaCore Function (Site not responding. Last check: 2007-10-25)
		The 8b/10b encoder takes byte inputs, and generates a direct current (DC) balanced stream (equal number of 1s and 0s) with a maximum run length of 5.
		Some of the individual 10-bit codes will have an equal number of 1s and 0s, while others will have either four 1s and six 0s, or, six 1s and four 0s.
		The 8B10B Encoder/Decoder MegaCore function can be used within generic framing procedure (GFP) applications.
	www.altera.com /products/ip/communications/codec/m-alt-ed8b10b.html (428 words)

	Computer Modules, Inc., PLDApplications, 8B10B encoder/decoder (Site not responding. Last check: 2007-10-25)
		PLDApplications Gigabit 8B10B core is a high-performance implementation of the physical coding sub-layer used in Gigabit Ethernet and Gigabit Fiber Channel transmissions.
		8B10B protocol is used to encode a 8-bit word stream to 10-bit codes that:
		Gigabit 8B10B core can directly connect user data source/receiver with market serializer/deserializer chips and is ideal for custom high-speed data links.
	www.compumodules.com /image-processing/pld-applications/plda-8b-10b-core.shtml (164 words)

	Fiber-Optic Encoding
		The 8B10B code used in 1000BASE-F Ethernet improves the DC balance by ensuring that the cumulative sum of ones and zeroes transmitted never differs by no more than three.
		Both 4B5B and 8B10B transmit one additional symbol for every four bits of useful data, amounting to an overhead of 25 percent.
		More elaborate codes like 64B65B substantially reduce the required overhead, and thus the number of symbols to be transmitted, but at the expense of simplicity and low latency.
	www.sigcon.com /Pubs/edn/FiberOpticEncoding.htm (795 words)

	Ethernet-Encoding-scheme (Site not responding. Last check: 2007-10-25)
		I know that for gigabit ethernet mostly the 8b10b encoding scheme is
		8b/10b is used for Gigabit Ethernet, 64b/66b for 10-Gigabit-Ethernet.
		8b/10b is usually done with a simple look-up-table,
	arch-fpga.gportalpage.com /Ethernet-Encoding-scheme-782770.html (441 words)

	Re: Clock Recovery from 8B10B encoded Data Stream
		Thomas, The DLL can not be used to extract clock, as the output is just the input, delayed.
		And finally, there are other designs using logic alone to recover the datastream of such a low bit rate stream in any of the Virtex family FPGAs (Xapp250, Xapp224).
		Clock Recovery from 8B10B encoded Data Stream, Thomas
	www.usenet.com /newsgroups/comp.arch.fpga/msg00562.html (270 words)

	[No title]
		HIGH-LEVEL ASSUMPTIONS ______________________ o Codings are based on 8B10B data codes (Dx.y) and special control characters (Kx.y) as defined in ANSI X3.230 FC-PH (Fibre Channel) Clause 11.
		8B10B TRANSMISSION CODE _______________________ o 8B10B transmission code provides the following functions: - Improves transmission characteristics - Enables bit-level clock recovery - Improves error detection - Separates data symbols from control symbols - Derives bit and word synchronization o 8-bit data bytes are encoded into 10-bit Data Characters.
		RUNNING DISPARITY _________________ 8B10B code recognizes the idea of a Running Disparity (the difference between the number of 1Õs and 0Õs transmitted).
	www.ieee802.org /3/z/public/presentations/july1996/RTglcod_31.txt (2481 words)

	LatticeSC Forums - SERDES
		The generic 8b10b core does not seem to retrain if it has a false lock
		Generic 8b10b PCS core datasheet or simulation model mismatch
		There are currently 2 guests browsing this forum, which makes a total of 3 users using this forum.
	www.latticesemi.com /forums/forum/categories.cfm?catid=214&entercat=y (77 words)

	Vitesse VSC7115 (Site not responding. Last check: 2007-10-25)
		The input of the VSC7115 should be 8B10B coded data, for which you may buy special chips such as the VSC7107.
		It is possible to implement the 8B10B coding circuit yourself; several projects at CERN have done this.
		The major problem for applications for the LHC experiment is that the input frequency should be exactly 53.125 MHz and not the 40 MHz that is commonly used in LHC.
	hsi.web.cern.ch /HSI/components/serialisers/vitesse/vsc7115.html (287 words)

	Answer Record # 16986: LogiCORE 8b10b Encoder v4.0 - Virtex, Block RAM-based exhibits incorrect behavior on DOUT, ...
		When I use the 8b10b Encoder v4.0 with Virtex and type set to Block RAM, incorrect results are reported on the DOUT, DOUT_B, and DISPOUT when I run behavioral simulation for both VHDL and Verilog.
		When you generate the 8b10b Encoder core for Block RAM-based Virtex, the start-up state for the core is all 0's, as defined in the Data Sheet.
		It incorrectly sets the initial state to the user-defined state defined in the GUI or in the XCO.
	www.xilinx.com /xlnx/xil_ans_display.jsp?getPagePath=16986&BV_SessionID=@@@@2093746349.1133456943@@@@&BV_EngineID=ccceaddgflghhedcefeceihdffhdfjf.0 (271 words)

	Semiconductor Applications —
		ASI Transmitter 8B10B Encoder The 8B10B encoder converts an 8-bit wide word to a 10-bit wide word.
		A 10-bit shift register loaded at the word rate from the encoder and unloaded at the bit rate of the LVDS output buffer is implemented for 8B10B Encoder Transmit PLL LVDS I/O Serial Data Serializer 108 Data 27 MHz Clock 4 Altera Corporation Preliminary ASI Reference Design Functional Description that function.
		8B10B Decoder The 8B10B decoder converts 10-bit wide parallel data from 8B10B codes into 8-bit wide raw data.
	www.semiapps.com /content.php?content_id=50621151626593037&taxo_id=160 (1609 words)

	Chuck Benz's ASIC/FPGA pages
		Here you will find an 8b10b encoder, a 8b10b decoder, and a
		Also, a table used by the testbench for the codes - this is raw 1's and 0's taken from a standard.
		8b/10b is of course now used for Fiberchannel, Gigabit Ethernet, 10Gigabit Ethernet, Infiniband, and PCI-Express.
	asics.chuckbenz.com (584 words)

	The Ultimate Phase-locked loop Dog Breeds Information Guide and Reference
		In order for this scheme to work, the data stream must have a transition frequently enough to correct any drift in the PLL's oscillator.
		Typically, some sort of redundant encoding is used; 8B10B is very common.
		Deskewing: If a clock is sent in parallel with data, that clock can be used to sample the data.
	www.dogluvers.com /dog_breeds/PLL (2124 words)

	LatticeSC Forums - Generic 8b10b PCS core datasheet or simulation model mismatch
		Topic Title: Generic 8b10b PCS core datasheet or simulation model mismatch
		Categories : SERDES : Generic 8b10b PCS core datasheet or simu...
		There are currently 1 guests browsing this forum, which makes a total of 2 users using this forum.
	www.latticesemi.com /forums/forum/messageview.cfm?catid=214&threadid=2361&enterthread=y (210 words)

	Alistair N Coles: A new 8B10B block code for high speed data transmission over unshielded twisted pair channels (HP ... (Site not responding. Last check: 2007-10-25)
		Alistair N Coles: A new 8B10B block code for high speed data transmission over unshielded twisted pair channels (HP Laboratories technical report)
		Alistair N Coles, "A new 8B10B block code for high speed data transmission over unshielded twisted pair channels (HP Laboratories technical report)", Hewlett-Packard Laboratories, Technical Publications Department, 1996.
		Other subject areas related to A new 8B10B block code for high speed data transmission over unshielded twisted pair channels (HP Laboratories technical report) (possibly beyond the scope of this Communications Systems Glossary) include: Code words, Data transmission systems.
	www.argospress.com /Resources/CommunicationsSystems/book-B0006QXX4S.htm (259 words)

	In telecommunication 8B10B is a line code that maps... (Site not responding. Last check: 2007-10-25)
		In telecommunication 8B10B is a line code that maps...
		A copy of the license is included in the section entitled
		A new 8B10B block code for high speed data transmission over unshielded twisted pair channels (HP Laboratories technical report) (HP Laboratories technical report)
	www.geodatabase.de /8B10B (158 words)

	L8104 Gigabit Controller (Site not responding. Last check: 2007-10-25)
		Consisting of a complete Media Access Controller for Layer 2 Gigabit Ethernet, the L8104 MAC contains an integrated 8B/10B PCS for fiber and short haul copper in Gigabit Ethernet systems.
		A unique and flexible control line interface makes this device Ideal as an Ethernet controller for Gigabit Ethernet switch ports, uplinks, backbones, and embedded designs for the LAN, WAN, SAN and Metro environments.
		The Controller consists of a 32-bit system interface, receive/transmit FIFO buffers, a full-duplex Ethernet Media Access Controller (MAC), an 8B/10B PCS, 10-bit Physical Layer Device (PHY) interface, and a 16-bit register interface.
	www.lsilogic.com /products/controllers/l8104.html (287 words)

	[isp-clec] Re: 8B10B - ISP-Australia Archive
		Ideally X and Y should be very close to 50.
		For example, for 8B10B, number of 1's in the output 10-bit block must be between 4 and 8.
		> > > > You can find out a lot about the 8B10B scheme by googling "Fibre Channel", if > > indeed that's the scheme in question.
	isp-lists.isp-planet.com /isp-clec/0211/msg00108.html (264 words)

	SOCcentral: Ingot Announces New 8B10B Encoder/Decoder Solution (Ingot Systems, Inc. 16698)
		John Miklosz, Ph.D. Ingot Announces New 8B10B Encoder/Decoder Solution
		October 17, 2005 - Ingot Systems, Inc. has announced the immediate availability of the IP7020, a new 8B10B Encoder/Decoder Solution which has been silicon proven and validated in an FPGA.
		It implements the physical coding sub-layer for Gigabit Ethernet and PCI-Express as defined in the ANSI X3.230-1994 and IEEE 802.3z specifications.
	www.soccentral.com /results.asp?entryID=16698 (220 words)

	Faction B8B10 (Site not responding. Last check: 2007-10-25)
		B8B10(flag) If flag is 1, encode each packet with a 8b10b code.
		Encodes each 8-bit byte into a 10-bit symbol with as many 0s as 1s.
		The point is to keep the BIM-4xx-RS232 radio happy.
	pdos.csail.mit.edu /~rtm/facdoc/B8B10.html (35 words)

	Untitled Document
		See channel coding absolute maximum ratings AC analysis Bode plot circuit filter.
		See tri-state buffer bus asynchronous buffer clock domain crossing defined fault I/O controller interface design example interface FSM design example microprocessor with cache network topology ripper, schematic diagram RS-485 network bypass capacitor.
		See microprocessor ceramic EPROM package resonator channel 8B10B coding 8B10B comma pattern bandwidth BER coding communication DMA FET.
	www.completedigitaldesign.com /toc/full-index.htm (1800 words)

	IEEE 1394 - Questionz.net , answers to all your questions (Site not responding. Last check: 2007-10-25)
		Further speed increases to 2 Gbit/s are planned.
		Other than the original FireWire 400 standard which used a data/strobe (D/S) encoding (called legacy mode) on the signal wires, FireWire 800 uses a data encoding scheme called 8B10B (also referred to as beta mode).
		Some expensive camcorders have included this bus since 1995.
	www.questionz.net /Apple_Macintosh/ILink.html (528 words)

	Ritter's Crypto Glossary and Dictionary of Technical Cryptography (Site not responding. Last check: 2007-10-25)
		Use a block code in which every codeword is balanced.
		Use a code in which most codewords are balanced, with a state machine to count the unbalance and correct it as soon as possible (e.g., 8b10b).
		Use a scrambler or simple Vernam cipher to randomize and statistically balance the data.
	www.isaicai.org /Harmony/2003-03/www.ciphersbyritter.com/GLOSSARY.HTM (11346 words)

	Serial Data Application Testing Program
		Designed from the ground up as complete compliance test solutions based on functional need, SDA-SAS and SDA-8B10B represent an innovative approach to signal integrity test and validation, according to Federico Lipparini, Director of Marketing, Performance Measurement Group for LeCroy.
		” SAS and 8B10B are the first two software applications benefiting from the BETA testing program undertaken earlier this year.
		It is because of the valuable input from lead users that LeCroy presents these software tools to the marketplace, ready to hit the ground running”.
	www.lecroy.com /ProductPress/FY06/050206.asp?news_id=856&menuid=40 (346 words)

	Ingot Systems, Inc.
		Santa Clara, Calif, Oct 17, 2005 - Ingot Systems, the leading provider of Electronic Design Solutions, today announced the immediate availability of the IP7020 a new 8B10B Encoder/Decoder Solution.
		The IP7020 IP Solution has been silicon proven and validated in an FPGA.
		• PCI Express/ Gigabit Ethernet 8B10B Coding Function
	www.ingotsys.com /product_announce_3.htm (297 words)

	Clock Recovery from 8B10B encoded Data Stream
		__Subject__: Clock Recovery from 8B10B encoded Data Stream
		Hello, has anyone already used a Spartan IIe DLL (PLL) to extract the clock out of a 100MBit/s 8B10B encoded data stream ?
		Will that work with a Spartan III DCM?
	www.usenet.com /newsgroups/comp.arch.fpga/msg00547.html (73 words)

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