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| | The AMD Athlon Processor |
 | | The AMD Athlon has a large dual-ported 128KB split-L1 cache (64KB instruction cache + 64KB data cache); a two-way, 2048-entry branch prediction table; multiple parallel x86 instruction decoders; and multiple integer and floating point schedulers for independent superscalar, out-of-order, speculative execution of instructions. |
 | | A logical one or zero is represented respectively by two voltage levels or the two states of a transistorized electronic switch (on or off like a light switch; a 1 or 0 in the binary number system, which, in turn, can be used to represent characters, decimal numbers, instructions, etc.). |
 | | Up to three MacroOPs, Athlon instructions, are sent from the decoders to the ICU per CPU cycle. |
| www.duxcw.com /digest/guides/cpu/athlon/athlon.htm (694 words) |
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