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	Industry Standard Architecture
		, standard> (ISA) A bus standard for IBM compatibles that extends the XT bus architecture to 16 bits.
		It also allows for bus mastering although only the first 16 MB of main memory is available for direct access.
		In reference to the XT bus architecture it is sometimes referred to as "AT bus architecture".
	burks.bton.ac.uk /burks/foldoc/95/56.htm (67 words)

	Industry Standard Architecture - Wikipedia, the free encyclopedia
		In reference to the XT bus, it is sometimes referred to as the AT bus architecture.
		The XT bus architecture is an eight-bit ISA bus used by Intel 8086 and Intel 8088 systems in the IBM PC and IBM PC XT in the 1980s.
		The PC/104 bus, used in industrial and embedded applications, is a derivative of the ISA bus, utilizing the same signal lines with different connectors.
	en.wikipedia.org /wiki/XT_bus_architecture (810 words)

	ISA bus: Industry Standard Architecture bus (Site not responding. Last check: 2007-10-12)
		Industry Standard Architecture (ISA) bus is the bus architecture used in the IBM PC and compatibles.
		The protocols also allows for bus mastering although only the first 16 MB of main memory is available for direct access.
		Starting in the early 90s, ISA began to be replaced by the PCI local bus architecture.
	www.javvin.com /hardware/ISABus.html (86 words)

	O'Reilly Network -- An Introduction to the InfiniBand Architecture
		The architecture is based on a serial, switched fabric that in addition to defining link bandwidths between 2.5 and 30 Gbits/sec, resolves the scalability, expandability, and fault tolerance limitations of the shared bus architecture through the use of switches and routers in the construction of its fabric.
		Version 1.0 of the InfiniBand Architecture Specification was released in October of 2000 and the 1.0a version, mainly consisting of minor changes to the 1.0 version, was released in June of 2001.
		The most common configuration of the PCI bus is a 32-bit 33MHz version that provides a bandwidth of 133MB per second, although the 2.2 version of the specification allows for a 64-bit version at 33MHz for a bandwidth of 266MB per second and even a 64-bit 66MHz version for a bandwidth of 533MB per second.
	www.oreillynet.com /pub/a/network/2002/02/04/windows.html (1993 words)

	AT bus (Site not responding. Last check: 2007-10-12)
		AT bus, also known as ISA (Industry Standard Architecture) bus, is a 16-bit bus started with the IBM-AT (Advanced Technology) systems.
		The bus is the collection of wires and electronic components that connect all device controllers and add-in cards.
		The bus, therefore, is the main highway for all data moving in and out of the computer.
	www.javvin.com /hardware/ATBus.html (77 words)

	A Bus Architecture For System-On-Chip Designs
		The CoreFrame on-chip bus architecture is defined along with examples to illustrate how a design friendly bus standard will effect the mix and match of reusable cores without sacrificing performance.
		Bus loading also limits theoreti-cal performance and the verification problems associated with bus loading can lead to a conservative design whose performance falls short of the inherent technology capa-bilities.
		On-chip bus architectures will make or break the concept of system-on-chip design if it provides an effective vehicle for the mix-and-match insertion of custom IP without sacrificing either performance or verification time.
	www.us.design-reuse.com /PAPERS/palmchip.html (2092 words)

	Personal Computer PC-AT Bus Description and ISA Pinout (Site not responding. Last check: 2007-10-12)
		The EISA bus (in one mode) used both edges of the clock, with the rising edge used to output address, and the falling edge to place the data on the bus.
		The PCI bus operates either synchronously or asynchronously with the "mother Board bus rate: The PCI bus is microprocessor independent.
		The bus drive was reduced from 24mA used on the ISA bus to 4mA for the embedded
	www.interfacebus.com /Design_Connector_PCAT.html (1305 words)

	Expansion Bus Architecture
		An 8-bit bus is characterized by a single slot that supports eight interrupts and four DMA channels, with all of them pre-assigned.
		The ISA bus is characterized by adding an additional short slot to a slot on the 8-bit bus to create the 16-bit connector.
		Introduced with the Pentium PC, PCI is a local bus architechture that supports either 32-or 64-bit bus, which allows it to be used with both 486 and Pentium computers.
	home.comcast.net /~teachcte/comp-rel/general/bus2.htm (731 words)

	The Computer Bus
		The bus is actually a set of circuits that run throughout the board and connect all the expansion slots, memory, and CPU, etc. together.
		The difference is that this bus connects directly to the system bus on the motherboard.
		Since the ISA bus is a max of 8mbps, it cannot keep the system bus fully occupied.
	www.footefamily.org /train/buses.htm (761 words)

	PC Bus Architecture
		The ISA bus is still a mainstay in many applications, despite the fact that it is largely unchanged since it was expanded to 16 bits in 1984!
		The bus implementations of the cards were originally based on information publishes in IBM AT Technical Reference and the ISA industry standard were written much later.
		The VLB is a 32-bit bus which is in a way a direct extension of the 486 processor/memory bus.
	www.richland.edu /staff/dkirby/pcbusarc.htm (3435 words)

	Halfbakery: Ethernet as Bus Architecture
		My first inclination is to point out that Ethernet is already a bus, however I'll put pedantry aside and point out instead that a packet switched internal network would be slower than anything in use now.
		The problem is that for almost every device in the system the gigabit bus will either be too slow, to expensive, or both.
		On an ethernet-style bus, every cache miss would require sending and receiving many bytes of addressing/routing stuff in addition to the actual data required.
	www.halfbakery.com /idea/Ethernet_20as_20Bus_20Architecture (1240 words)

	Analyzing Bus Architectures for ARM-based SOC Designs
		The performance bottleneck of multiprocessor-based SoC designs is often limited by the bus architecture and topology that is chosen.
		Finding an efficient bus architecture early in the design can be not only difficult but critical to achieve the desired system performance while balancing to keep cost, power and area requirements to a minimum.
		This seminar presents a simulation-based approach for profiling and analysis to identify bottlenecks within a design's bus architecture; it also explains the impact that these bottlenecks have on the overall performance and throughput of the design.
	www.mentor.com /products/fv/events/bus_architectures.cfm (149 words)

	Data Bus
		Systems Interface Bus (SIB) SIB is a proprietary bus structure, developed for earlier modifications in the B-52 and limited high performance applications.
		Industry Standard Architecture (ISA) bus This bus architecture was developed by IBM for the PC/XT and PC/AT and adopted for industrial applications.
		The ISA architecture is a defacto standard, still in wide use where high performance is not necessary.
	www.fas.org /man/dod-101/sys/ac/equip/bus.htm (806 words)

	The Allayer RoX® Bus Architecture
		When the first RoX bus devices were introduced in early 1998, the concept of the RoX bus was quickly proven in the field with numerous systems using the AL100 as the basis of an expandable Fast Ethernet switching family.
		With the recent introduction of the RoX-compatible AL1000 Gigabit Switching IC, the architecture has now been shown to be up to the rest of the task: it is now a high performance, scalable inter-chip architecture that can support Ethernet, Fast Ethernet and Gigabit Ethernet switching systems in all configurations.
		With the RoX bus as a switching fabric, the Allayer Switch ICs (including the AL100, AL101, AL300 and AL1000) can be used to configure a wide range of high performance Fast Ethernet, Gigabit Ethernet and hybrid switches in both managed and unmanaged configurations.
	www.amslink.com /allayer99/ab001.html (1323 words)

	The Math Forum - Math Library - Architecture (Site not responding. Last check: 2007-10-12)
		AIE uses architecture as the basis for hands-on, interactive projects that connect, integrate and deepen K-12 student learning across the curriculum.
		A unit about architecture and its unique relation to mathematics, incorporating the study of such mathematical concepts as ratio, proportion, scales, symmetry, and similarity, and providing definitions and explanations of the mathematical concepts of...more>>
		To produce structures that are functional as well as models of architectural beauty, designers must apply principles of mathematics in their work.
	mathforum.org /library/topics/architecture (2240 words)

	Apple - Power Mac G5 - Architecture
		Consider the 1GHz frontside bus, for instance: There’s one on each processor for maximum throughput to and from the PowerPC G5 processor.
		Add to that the 400MHz, dual-channel 128-bit memory bus, AGP 8X Pro graphics bus — as well as the HyperTransport interface that connects the PCI-X controller and the I/O subsystems to the system controller — and you’re looking at some impressive architectural advances that speed up the data flow inside your computer.
		As an advanced engineering concept, it’s beautiful in its simplicity: A point-to-point architecture provides each primary subsystem with dedicated throughput to main memory, neatly avoiding time-consuming contention for bandwidth (unlike subsystems that share a bus and are compelled to constantly negotiate for access and bandwidth across a common data path).
	www.apple.com /lae/powermac/architecture.html (975 words)

	SYSTEM UNIT
		This architecture has a small number of instructions built into the circuits and if those basic instructions are made to execute faster, then RISC computers increase performance.
		Open Architecture: This architecture is a system whose specifications are made public to encourage third-party vendors to develop add-on products for it.
		This is a bus standard for PCs that extends the AT bus (the ISA bus) architecture to a 32-bit bus.
	home.olemiss.edu /~misbook/hm2.htm (1854 words)

	Pentium 4: More speed in the pipeline \| Tech News on ZDNet (Site not responding. Last check: 2007-10-12)
		Among other tasks, the chipset creates a data path, or system bus, between the processor and a computer's memory.
		Overall, the increase in bus speed could boost performance by 3 percent to 5 percent, he said.
		Both approaches have their advantages, but at this point "there are so many different factors...it is hard to determine" which will prove superior at any given speed, Brookwood said.
	zdnet.com.com /2100-1103-980206.html (839 words)

	Apple - PowerPC G5 - Architecture
		And in fact, the forward-looking G5 architecture scales to meet memory requirements for the next twenty years, even if they double every year.
		In addition to providing fast access to main memory, this high-performance frontside bus architecture lets each G5 discover and access data in the other processor’s cache.
		The PowerPC architecture was designed from the get-go for both 32- and 64-bit processing.
	www.apple.com /lae/g5/architecture.html (677 words)

	Cray Inc - The Supercomputer Company > Products > XD1 > DCP Architecture (Site not responding. Last check: 2007-10-12)
		Cray’s Direct Connected Processor (DCP) architecture addresses these limitations by fusing the processor directly to the interconnect fabric, eliminating memory contention and PCI bus bottlenecks.
		The directed connected processors architecture applies to systems where processors are tied directly into a message passing, switched interconnect.
		Cray's implementation of the DCP architecture optimizes message-passing applications by directly linking processors to each other through a high performance interconnect fabric, eliminating shared memory contention and PCI bus bottlenecks.
	www.cray.com /products/xd1/architecture.html (462 words)

	VARBusiness (Site not responding. Last check: 2007-10-12)
		The workstation features a modern crossbar architecture to eliminate problems that a shared bus architecture encounters, greatly speeding up overall performance of the workstation in data- and compute-intensive operations.
		The balanced architecture provides end users with all the processing power, memory, I/O and graphics that is required of a graphics workstation.
		A modular architecture uses a crossbar-switching matrix and provides a system architecture with low latency and high bandwidth.
	www.varbusiness.com /sections/98pages/206cov_unix.jhtml (372 words)

	Parker Hannifin, Compumotor Division, North America - A Complete Family of Motion Control Products
		Questions arise as to what bus architecture is needed.
		Each bus architecture must have a unique motion control board specifically designed to operate with it.
		Problems are compounded when a new bus architecture is specified.
	www.compumotor.com /literature/pg038_ethernet_mc.htm (514 words)

	MXIbus Multisystem Extension Interface Bus Specification - April 1997 - Manuals - Support - National Instruments
		The Multisystem eXtension Interface bus (MXIbus) is a multidrop parallel bus architecture designed for high-speed communication between devices.
		The MXIbus architecture is a very high-performance link between devices because it maps actual bus cycles on one device to bus cycles on another device.
		Because it is a multidrop, multimaster architecture with a full 32-bit multiplexed address and data pathway, multiple 8-, 16-, or 32-bit MXIbus devices can dynamically communicate with each other and control each other’s resources at very high speeds.
	digital.ni.com /manuals.nsf/websearch/9062881C4D637C7B8625665F005DA47E (261 words)

	Intel® Itanium® 2 Processors Get Faster Bus Architecture
		Servers designed to utilize the new bus are expected to deliver more than 65 percent greater system bandwidth over servers designed with current Itanium 2 processors with a 400 MHz FSB.
		The improved front side bus bandwidth allows for 10.6 gigabits of data per second to pass from the processor to other system components.
		The ability to move more data in a very short period of time is critical to compute intensive applications in the scientific, oil and gas and government industries.
	www.intel.com /pressroom/archive/releases/20050718comp.htm (613 words)

	IBM Redbooks \| Patterns: Implementing an SOA using an Enterprise Service Bus
		Many of these enterprises are determined to use proven architectures, designs and product mappings in order to speed their implementation and minimize their risk.
		This IBM Redbook focuses on how the service-oriented architecture profile of the Process Integration patterns can be used to start implementing service-oriented architecture using an Enterprise Service Bus.
		Router and Broker interactions within an Enterprise Service Bus are covered, along with off-the-bus service choreography and the Exposed ESB Gateway to enable interaction in an inter-enterprise environment.
	www.redbooks.ibm.com /abstracts/sg246346.html (1050 words)

	What is Micro Channel Architecture? - A Word Definition From the Webopedia Computer Dictionary
		It is called a bus architecture because it defines how peripheral devices and internal components communicate across the computer's expansion bus.
		Introduced by IBM in 1987, MCA was designed to take the place of the older AT bus, the architecture used on IBM PC-ATs and compatibles.
		For a variety of reasons, however, the industry never accepted the new architecture.
	www.webopedia.com /TERM/M/Micro_Channel_Architecture_MCA.html (84 words)

	PC Bus to STD Bus Interface - PC-STD ADP
		STD Bus SYSRESET controlled by the PC-XT/AT The PC-STD Adapter is a low cost solution that permits an IBM PC-XT/AT or compatible host computer access to the IEEE 961 STD Bus I/O cards for industrial applications.
		The host PC-XT/AT is coupled directly to the STD Bus via a 2 card set.
		Once card is installed in the PC-XT/AT and the other is an STD Bus card enclosure connected by two 34-pin ribbon cables.
	www.stdbus.com /products/std/pcstdadp.html (206 words)

	System sizing (Windows Server 2000 family) (Site not responding. Last check: 2007-10-12)
		The bus architecture in single and multiprocessor systems also affects system performance.
		The ISA (AT bus) architecture is low bandwidth and is not recommended for a Terminal server.
		Use a higher-performance bus, such as EISA, MCA, or PCI for best performance.
	www.microsoft.com /windows2000/en/advanced/ts_pln_c_020.htm (434 words)

	My-ESM - Intel unwraps 400-MHz front-side-bus architecture
		Unlike the P6 architecture, the new FSB divides each clock cycle to achieve a much higher speed.
		Albert Yu, senior vice president of Intel's architecture group, said the new architecture will allow the arithmetic logic unit to run at different speeds.
		The SIMD bus has also been increased from a 64- to a 128-bit word width to offer the highest streaming graphics and audio performance with the most security.
	www.ebnews.com /story/OEG20000822S0029 (313 words)

	PCI Expansion Bus Architecture
		PCI (Peripheral Component Interconnect) is a high-performance expansion bus architecture that was originally developed by Intel to replace the traditional Industry Standard Architecture (ISA) and Enhanced Industry Standard Architecture (EISA) buses found in many 80x86-based PCs.
		In addition, the PCI bus will allow Apple to use more industry-standard components in the future, which will make Power Macintosh computers and Workgroup Servers even more affordable.p PCI provides high performance.
		Plans for extending the bus include support for 64-bit extensions and a higher clock speed across the bus.
	www.mug.jhmi.edu /mirrors/InfoAlley/0995/18/pci.html (1001 words)

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