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Topic: Address bus

Related Topics

Memory management unit

NS32032

Opcode

Intel 8080

65816

Instruction set

VAX

	Use of deferred bus access for address translation in a shared memory clustered computer system - Patent 5682512
		If the global address to which access is requested by the bus agent does not correspond to a local address, as determined by the address translation and control circuit, then the global address access request is passed to the bridge input/output circuit for communication of the request to the second node.
		In this case the global address of the request is passed to the address translation and control circuit and, if the global address corresponds to a local address of the node, a local address access request is issued on the bus using a local address corresponding to the received global address.
		The requested address is passed to the address decode and translation circuit 58, which determines whether the requested address is within the re-mapped global address space corresponding to the fixed address space for the local node, by reference to the information provided in the address translation table memory 60.
	www.freepatentsonline.com /5682512.html (8152 words)

	Bus switch coupling for series-coupled address bus sections in a microprocessor - Patent 4016546
		The bus control and coupling circuitry as recited in claim 2 further including preconditioning means coupled to each of said bus conductors of said second group and to said control means for presetting each of said bus conductors of said second group to a predetermined level under control of said control means.
		The first address bus section is further split by means of an address bus switch which controllably couples each conductor of the first address bus section to a corresponding conductor of a third address bus section.
		In extended addressing, the address contained in the second byte of the instruction is used as the higher eight-bits of the address of the operand.
	www.freepatentsonline.com /4016546.html (8511 words)

	Software-Based Memory Testing - Address Bus Test
		These addresses are analogous to the set of data values used in the walking 1's test.
		The first parameter is the base address of the memory block to be tested and the second is its size, in bytes.
		If the address bus test fails, the address at which the first error was detected will be returned.
	www.esacademy.com /faq/docs/memtest/address.htm (733 words)

	PC bus systems
		Bus masters are devices capable of initiating any bus cycle (memory read/write, port addressing, etc.) and bus slaves are devices which are not capable of initiating a bus cycle but merely responding to it.
		The bus mastering was not a complete or perfect implementation due to certain limitations such as a request by a Bus master for 'Bus hand-off' requiring several cycles for completion and the master having to relinquish the bus periodically to allow memory refresh (or do the refresh itself).
		This duplication was necessary because the address lines on the XT bus were latched (the address signals were tied to flip-flops which maintained the address lines logic level until explicitly set to a different value) and this latching process caused propagation delays that would slow down peripheral boards.
	www.csn.ul.ie /~stephen/buses.html (7161 words)

	Bus
		A bus is a set of signal pathways that allow information to travel between components inside or outside of a computer.
		It will select the particular memory address that the device is using and use the address bus to write to that particular address.
		When this bus was originally released it was a proprietary bus, which allowed only IBM to create peripherals and the actual interface.
	www.escotal.com /bus.html (545 words)

	Fast Accurate Memory Test Suite - RAM, SRAM, DRAM, address bus, data bus
		The address and data lines are used to select the memory location and to transfer the data, respectively.
		That's because the address bus test assumes a working data bus, and the device test results are meaningless unless both the address and data buses are known to be good.
		By looking at the data value or address at which the test failed, he or she should be able to quickly isolate the problem on the circuit board.
	www.netrino.com /Articles/MemoryTesting (4125 words)

	Processor / Memory Address Bus
		The address bus is the set of lines that carry information about where in memory the data is to be transferred to or from.
		The speed of the address bus is the same as the data bus it is matched to.
		Address bus size is not something that is thought of very often, because it has no direct impact on performance.
	www.pcguide.com /ref/cpu/arch/extAddress-c.html (357 words)

	Bus error - Wikipedia, the free encyclopedia
		In computing, a bus error is generally an attempt to access memory that the CPU cannot physically address.
		Bus errors can also be caused by any general device fault that the computer detects.
		The term bus error is also sometimes used [1] to refer to some critical member of a team becoming unavailable because of catastrophe, as in being "hit by a bus".
	en.wikipedia.org /wiki/Bus_error (525 words)

	CmpSci 535 Lecture 10
		The bus adapter provides a connection to an asynchronous bus that is constrained to matching the characteristics of the synchronous bus.
		Usually, in such architectures, the synchronous bus is a custom design that is found only on the CPU board itself, and possibly on memory expansion daughter cards, although systems have been designed in the past with such buses on custom backplanes to facilitate memory expansion.
		One problem with multiplexing the address lines with data values, is that they must then pass though an extra set of steering logic gates that direct the signals to the appropriate places at each end of the transmission.
	www.cs.umass.edu /~weems/CmpSci535/535lecture10.html (4725 words)

	General Purpose ISA Interface Card
		In practice, addresses are flying by on the ISA bus all the time, and it's very important that an adapter card does not interfere with the data bus until the processor actually wants it to.
		The I/O adapter card needs to wait until AEN is low before it becomes active and thinks the address on the address bus is selecting it, or else it will find itself being erroneously selected by ongoing DMA activity, which also uses the ~IOR line, but not in conjunction with an address.
		The ten lowest address lines, A0-A9, need to be decoded in order to select one of 1024 ports that the card will respond to, and the data bus must be buffered so that the card will not interfere with existing signals on the data bus lines when the card is not selected.
	www.cryogenius.com /hardware/isacard (1060 words)

	Bus Cycles
		If it's instruction set and bus width were the same as a Z80 (dear Intel - please forgive me!), it would run at twice the speed of the 4 T state Z80 at the same clock rate.
		Bus width reduces machine cycles by doing more at once; transistors shorten long machine cycles by completing complex operations faster.
		Often it's all but impossible to tell what the CPU is doing by watching the bus, unless you notice that fetches generally are from increasing addresses (programs execute from low addresses to higher ones, unless there's a program transfer), while memory reads occur much less frequently, generally from addresses not near the code.
	www.ganssle.com /articles/abuscyc.htm (2554 words)

	addresses from FOLDOC
		The CPU outputs addresses on its address bus which may be connected to an address decoder, cache controller, memory management unit, and other devices.
		Indirect addressing modes often have options for pre- or post- increment or decrement, meaning that the register or memory location containing the effective address is incremented or decremented by some amount (either fixed or also specified in the instruction), either before or after the instruction is executed.
		The size of a processor's address space depends on the width of the processor's address bus and address registers.
	foldoc.org /?addresses (1216 words)

	What is bus? - A Word Definition From the Webopedia Computer Dictionary
		This is a bus that connects all the internal computer components to the CPU and main memory.
		On PCs, the old ISA bus is being replaced by faster buses such as PCI.
		The local bus is a high-speed pathway that connects directly to the processor.
	www.webopedia.com /TERM/b/bus.html (666 words)

	Address bus - Wikipedia, the free encyclopedia
		The width of an address bus, along with the size of addressable memory elements, determines how much memory can be accessed.
		For example, a 16-bit wide address bus (commonly used in the 8-bit processors of the 1970s and early 1980s) reaches across 2
		In most microcomputers the addressable elements are 8-bit bytes (so a "Ki" in that case is equal to a "KiB", i.e.
	en.wikipedia.org /wiki/Address_bus (221 words)

	What is address bus? - A Word Definition From the Webopedia Computer Dictionary
		A collection of wires connecting the CPU with main memory that is used to identify particular locations (addresses) in main memory.
		The width of the address bus (that is, the number of wires) determines how many unique memory locations can be addressed.
		Modern PCs and Macintoshes have as many as 36 address lines, which enables them theoretically to access 64 GB (gigabytes) of main memory.
	webopedia.internet.com /TERM/A/address_bus.html (114 words)

	Software-Based Memory Testing - graduate research paper
		This happens because an address bit that is shorted or open causes the memory device to see a different address from the one selected by the processor.
		However, since address bus failures are just as likely to occur as data bus failures, these tests are essentially worthless.
		That is because the address bus test assumes a working data bus, and the integrity test results are meaningful only if both busses are working properly.
	www.netrino.com /Articles/MemoryTesting/paper.html?the_id=49 (3630 words)

	Embedded.com - Introduction to direct memory access
		To avoid bus contention, the bus buffer used by the DMA device must not drive the address bus until after HLDA goes active to indicate that the CPU has stopped driving the bus signals, and it must stop driving the bus before the CPU drives HLDA inactive.
		Typical setup parameters include the base address of the source area, the base address of the destination area, the length of the block, and whether the DMA controller should generate a processor interrupt once the block transfer is complete.
		In burst mode, the DMA controller keeps control of the bus until all the data buffered by the requesting device has been transferred to memory (or when the output device buffer is full, if writing to a peripheral).
	www.embedded.com /showArticle.jhtml?articleID=15300200 (1301 words)

	address bus (Site not responding. Last check: 2007-10-03)
		Address bus is an internal channel from the CPU to memory across which the addresses of data are transmitted.
		The number of lines or wires in the address bus determines the amount of memory that can be directly addressed as each line carries one bit of the address.
		For example, If the address bus contains n electrical lines, the processor can address up to 2**n unique locations.
	www.javvin.com /hardware/AddressBus.html (67 words)

	VME Bus Description, Pinout and Standards information
		Revision C allowed 64 bit Data transfers, with the upper 32 data bits being multiplexed onto the address bus once the address cycle was complete (after the address was broadcast) during Block Transfers (BLT).
		The Address bus width used by the Master is determined by the setting of the Address Modifier [AM] codes.
		Under the latest bus specification (which added the 160 pin connector) either connector may be used (but I believe both have to be the same type).
	www.interfacebus.com /Design_Connector_VME.html (3079 words)

	Bus
		When referring to a computer, the bus also known as the address bus, data bus, or local bus is a data connection connection between two or more devices connected to the computer.
		A bus is capable of being parallel or a serial bus and today all computers utilize two types of buses, an internal or local bus and an external bus.
		An internal bus enables a communication between internal components such as a computer video card and memory and an external bus is capable of communicating with external components such as a SCSI scanner.
	www.computerhope.com /jargon/b/bus.htm (219 words)

	Address Bus Tests Z-80
		In the event an addressing error is suspected, the following test group can troubleshoot and verify each address line individually.
		Testing each position is done by selecting the appropriate test, and measuring the response with an oscilloscope, or the external probe.
		All addressing errors can be pinpointed using these tests, and any board submitted for repair shall undergo these procedures, if needed, to be certified error-free by GLS1 Electronics.
	gls1electronics.com /address_bus_tests__z80.htm (211 words)

	address bus (Site not responding. Last check: 2007-10-03)
		The electronic channel, usually from 20 to 64 lines wide, used to transmit the signals that specify locations in memory.
		The number of lines in the address bus determines the number of memory locations that the processor can access, because each line carries one bit of the address.
		A 20-line address bus (used in early Intel 8086/8088 processors) can access 1MB of memory, a 24-line address bus can access 16MB, and a 32-line address bus can access more than 4GB.
	www.coffeycountyks.org /Terms/2461HTML-51.html (93 words)

	Address bus control apparatus (US5148539)
		An address bus control apparatus links a memory bus connected with a CPU and a memory unit and a system bus connected with input/output units.
		The address bus width of the system bus is smaller than that of the memory bus and one of the input/output units is a master unit using address data of a smaller width than the address bus width of the system bus for accessing another unit.
		first storing means for storing first predetermined address information having a width corresponding to a predetermined difference between the address information width of said accessing unit and the width of said first address bus; and
	www.delphion.com /details?pn10=US05148539 (322 words)

	My-ESM - IMI's clock generators timed to address bus mismatch in Solano chipset
		Meanwhile, built-in tolerances in the chip are being targeted both at OEMs and the rogue community of microprocessor overclockers.
		The clock chips drive the Intel 815's frontside processor bus and SDRAM interface, as well as the associated PCI bus, AGP bus, USB bus, and the low-pin-count, or IOAPIC, bus now used internally to replace the defunct ISA bus.
		The Dial-a-Frequency feature, for example, can be used to set the frontside processor bus at any frequency, including the standard 66.66-, 100-, and 133.33-MHz speeds of the Intel 815.
	www.my-esm.com /digest/story/OEG20000522S0017 (621 words)

	Address Bus Definition, What is Address Bus
		Know matter if you need to know "what is a Address Bus", the definition of a "Address Bus", or the meaning of a "Address Bus", you can find it here at Network Liquidators.
		There's quite a bit of information out there to learn, and it all starts by you having the initiative to seek out that information.
		We hope this definition of Address Bus was what you were looking for and appreciate your visit and welcome you back anytime.
	www.networkliquidators.com /definition-address-bus.asp (600 words)

	Video address bus issue with Linux install - Parallels Support Forum
		During the agp detection, Debian detects the intel i815 chipset but then returns a kernal panic stating that "gatt bus addr too high" I'm taking this to mean that the video controller's bus address is out of range of a "normal" x86 architecture.
		In my particular problem, I installed Slackware without a hitch but upon first reboot, the kernel would panic and complain about the bus error your mentioned in your first post.
		agpgart: gatt bus addr too high<3>agpgart: error configuring host chipset.
	forum.parallels.com /thread1931.html (1020 words)

	Dictionary of Computers - address bus
		Electrical wires within the computer that connect the central processing unit (CPU) and memory, and are used to represent specific locations (the address) in the memory.
		Used in conjunction with the electrical pathways, the control bus, and data bus.
		White stands for the snow which covers the ground for 5—7 months each year.
	www.tiscali.co.uk /reference/dictionaries/computers/data/m0034256.html (188 words)

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