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| | ATLAS I Overview Transparencies (ICS-FORTH, ATM switch) |
 | | Architecture of ATLAS I: The ATM cells themselves are stored in the (single) shared cell buffer, and are never moved until they depart. |
 | | ATLAS I links can be bundled together, in groups of 2, behaving like a 1.24 Gb/s link, or in groups of 4, providing the equivalent of 2.5 Gb/s links, or in groups of 8, giving 5.0 Gbps/link. |
 | | The switch part of this architecture must solve a matching problem during each cell time: for each input buffer, choose one of the cell colors present in it, so that no two input buffers have the same color chosen, and so that the number of colors chosen is maximized (or other performance criteria, e.g. |
| archvlsi.ics.forth.gr /atlasI/gen_talk1.html (1426 words) |
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