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| | Patent 4025903 |
 | | In case a memory unit is included in the processor, account is taken of this fact and, for all practical purposes, the starting and ending addresses of each module are increased by the memory capacity LMCO of the memory unit in the processor. |
 | | The local memory capacity LMC, which is impressed on the input terminals A1, A2, A3, and A4 of the adder ADR, is reproduced at the output terminals, thus producing a pseudo-or spurious upper limit at the output of the adder. |
 | | Where a memory unit MUNP is installed in the processor and is used as part of the memory bank, the starting capacity, which represents the capacity of that memory unit, may be set in a local memory capacity register LMCRP and the output applied directly to a parallel-to-serial shift register PSSRP as indicated in FIG. |
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