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| | Fourth-order digital multiplex system for transmitting a plurality of digital signals at a nominal bit rate of 44 736 ... (Site not responding. Last check: 2007-10-13) |
 | | As signal processing in transmitter 1 is effected on the basis of signals in the normal binary code, each of the three B3Zs coded signals D1, D2, D3 is applied to a B3Zs-adapter 4, in which after regeneration by means of a recovered clock signal a conversion into a binary signal is effected. |
 | | Each of the binary signals d1, d2, d3 thus obtained is applied together with the associated clock signal to a jitter reducing unit 5, in which the value of the peak-to-peak jitter amplitude, depending on the jitter frequency, is reduced to approximately 1.5 UI. |
 | | A second reason is that differences of frequency between the tributary bit streams which may be received from independent sources, and the system clock for the higher-order bit stream must be coped with. |
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