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Topic: Bit synchronous operation

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	Glossary of Electronic and Engineering Terms
		Note 1: Examples of bit error ratio are (a) transmission BER, i.e, the number of erroneous bits received divided by the total number of bits transmitted; and (b) information BER, i.e., the number of erroneous decoded (corrected) bits divided by the total number of decoded (corrected) bits.
		Note: For n-ary operation, the bit rate is equal to log n times the rate (in bauds), where 2 n is the number of significant conditions in the signal.
		Bit synchronous operation: Operation in which data circuit terminating equipment (DCE), data terminal equipment (DTE), and transmitting circuits are all operated in bit synchronism with a clock.
	www.interfacebus.com /Engineering_Dictionary_2.html (621 words)

	Synchronous Communications Adapter (Site not responding. Last check: 2007-11-02)
		STR operation in a four-wire, full-duplex facility requires that idle characters be transmitted on the pair of wires that is not passing intelligent data.
		The 1.25-second timer is used in the synchronize mode to signal the end of the transmission of idle characters for synchronization in the STR mode.
		In noncentralized operation, the operation is similar to centralized operation except the selected station (after being polled) must respond with its address and the address of the station to which it wishes to transmit.
	www.ibm1130.net /functional/SCA.html (8416 words)

	Telecom Dictionary B: Phone Service Definitions
		Bit Robbing - In digital carrier systems, the practice or technique of preempting, at regular intervals and for the purpose of transmitting signaling information, one digit time slot that (a) is associated with the given user channel for which signaling is required, and (b) is used primarily for transporting encoded speech via that channel.
		Bit robbing is acceptable for voice conversations or data transmissions that are received by a modem but not for "pure" data transmission (where every bit is significant).
		Bits with a value of 0 are represented by a no-voltage time slot.) If more than 15 bits in a row are sent with a 0 value, this "lull" in 1 bits that the system depends on for synchronization may be long enough for two end points to become out of synchronization.
	www.higginsinternational.com /Definitions/telecom_dictionary_b.html (11646 words)

	Counters (2)
		Synchronous digital counters have a common clock which results in all the flip-flops being triggered simultaneously.
		The count sequence produced by synchronous counters is not dependent on the trigger characteristics of the flip-flops that comprise the count stages.
		To define the counter operation of synchronous counters we may employ a procedure similar to that used in the analysis of asynchronous counters.
	scitec.uwichill.edu.bb /cmp/online/P10F/counters1.htm (592 words)

	IDT Begins Volume Shipments of 0.18-Micron Products \| IDT
		IDTâs synchronous dual-port family includes a 3.3-volt core with selectable 3.3-volt or 2.5-volt I/Os which provides designers with the flexibility needed to combine legacy components with 2.5-volt system components such as DSPs or microprocessors.
		The dual-ports feature a synchronous interface, with independent clocks on each port that are able to run at different frequencies.
		This ability to accommodate two independent random operations makes the chips useful as buffers in networking applications where an incoming stream of data is stored, while at the same time a previously stored block of data is processed.
	www.idt.com /?id=894 (945 words)

	Asynchronous 40-bit TTL CPU
		In a "normal" synchronous processor, the speed is often limited by the speed of the slowest part.
		Only 32 bits are considered, cause this barrel shifter is meant to be used in the floating point unit to normalise the fractional part.
		The normalise block is used after a floating point operation to left-shift the result, incrementing the exponent field accordingly, so that the most significant bit of the floating point fractional field is a "1".
	www.hanssummers.com /computers/ttlcpu/index.htm (3732 words)

	S/390 Parallel Enterprise Server CMOS Cryptographic Coprocessor
		The instruction operation code and all operand data (general-purpose register data and/or storage data) are then transferred to the SCM over the data bus for actual instruction execution within the SCM.
		Communication between the CPU and the SCM for these asynchronous operations is executed by means of messages which pass through a queue and are sent to and from the SCM.
		There are two sizes of C-SRAM: The first is 64 elements by 73 bits and is used for the key buffer, key part, signature-object master key, and receive-object master key arrays; the second is 512 elements by 73 bits, which is used twice to make a logical 1024-element PKA array.
	www.research.ibm.com /journal/rd/435/easter.html (7188 words)

	Operations
		In order to ensure an efficient and optimum use of the system resources and to guarantee the achievement of the mission objectives Envisat reference mission operation profiles are established and used for mission and system analyses to define the instrument operational strategies, the command and control, and the data transmission, processing and distribution scenarios.
		The global mission operation strategy is intended to provide the maximum coverage of the Earth components (atmosphere, ocean, ice, land) relevant to each payload instrument.
		MERIS RR is systematically operated and recorded on board for the duration of the sun-illuminated segment.
	earth.esa.int /envisat/m-s/mission/operations.html (2271 words)

	Linux.com - Text-Terminal-HOWTO: Appendix C: Serial Communications on EIA-232 (RS-232)
		Since there is no signal to mark the boundaries between these bits, the only effect of the 2nd stop bit is that the line must remain at -12 V idle twice as long.
		An additional parity bit may (or may not) be appended to this resulting in a byte length of 7, 8 or 9 bits.
		For the receiver to detect individual bits it must always have a clock signal which is in synchronization with the transmitter clock.
	www.linux.com /howtos/Text-Terminal-HOWTO-22.shtml (2928 words)

	[No title]
		The bit stream is examined on a bit-by-bit basis for the binary sequence 01111110 (hexadecimal 0x7e).
		Asynchronous to Synchronous Conversion There may be some use of asynchronous-to-synchronous converters (some built into modems and cellular interfaces), resulting in an asynchronous PPP implementation on one end of a link and a synchronous implementation on the other.
		A serial bit stream is transmitted on the wire, the FCS is calculated over the serial data as it goes out, and the complement of the resulting FCS is appended to the serial stream, followed by the Flag Sequence.
	ietf.org /rfc/rfc1662.txt (4458 words)

	Administration Guide
		The operation takes a variable from the origin and performs one of four selected operations on a variable from the target and replaces the target variable with the results of the operation.
		LAPI_Fence is a local operation which is used to guarantee that all LAPI operations initiated by the local process and the same process thread are complete.
		LAPI_Init and LAPI_Term operations are used to initialize and terminate the communication structures required to effect LAPI communications for a specific instance of LAPI.
	www.nersc.gov /vendor_docs/ibm/pssp/admin/am0a0mst197.html (1275 words)

	Product Folder - Fairchild P/N DM74AS161 - Synchronous 4-Bit Binary Counter with Asynchronous Clear
		Synchronous operation is provided by having all flip-flops clocked simultaneously so that outputs change coincident with each other when so instructed by count enable inputs and internal gating.
		As presetting is synchronous, setting up a low level at the LOAD# input disables the counter and causes the outputs to agree with set up data after the next clock pulse regardless of the levels of enable input.
		The DM74AS163 clear function is synchronous; and a low level at the clear input sets all four of the flip-flop outputs LOW after the next clock pulse, regardless of the levels of enable inputs.
	www.fairchildsemi.com /pf/DM/DM74AS161.html (632 words)

	Implementing Bit-addressing with Specialization
		This operator takes two dynamic values and returns a static value; the compiler returns true only if it can prove the values will be equal, this is positive alias (sharing) information.
		Thus the status of a line may be either clean or a mask indicating which bits are dirty and which are not present in the cache at all.
		The delay operator returns a signal of the same length as its input, thus it loses the last sample of the input signal.
	www.cs.cmu.edu /afs/cs.cmu.edu/usr/spot/web/bit-addr/bit-addr.html (5061 words)

	VLSI Digital Circuits (CSE 477) (Site not responding. Last check: 2007-11-02)
		The decimation filter is composed of filtering and decimation operation blocks for both direct and polyphase approaches, which are realized by the following basic multipliers, adders and synchronous reset flip-flops.
		One is the direct implementation of filtering and decimation operation, and the other is polyphase implementation, which has computationally efficient architecture.
		However, since E0(z) and E1(z) are operating at the lower rate, only a total of (3+1)/2 multiplications and 3/2 additions per unit time are required.
	www.cse.psu.edu /~joolee/CSE477/prototype.htm (630 words)

	Technical Q&A DV14: Synchronous SCSI Operation
		A: The term "Synchronous SCSI" is often confused with invoking the SCSI Manager synchronously.
		In synchronous mode, the sending device is permitted to send the next byte without receiving acknowledgment that the receiving device actually received the last byte.
		Synchronous SCSI transfers are not supported with the old SCSI manager.
	developer.apple.com /qa/dv/dv14.html (249 words)

	Operations and Data Acquistion for TIMAS
		The total volume of data collected into the spin buffer during each spin period (26,880 x 16 bits = 430,080 bits) is far greater than the total telemetry allocation to the TIMAS instrument (~4,100 bps x 6s = 24,600 bits) without consideration of the mass spectra and other essential data such as singles count rates.
		The total instrument operation is phased with an internal spin frame counter from which we define a Super-Spin (SS) period of 32 spins (~ 3.2 min).
		The Rice compression scheme relies on patterns in the bit stream and its efficiency is strongly dependent on the characteristics of the data.
	lasp.colorado.edu /timas/operations.html (3223 words)

	BRL Report 1964
		Operational maintenance is possible by "on call basis" due to high reliability.
		The TRW control computer system is used primarily to compute various unit operations factors, to monitor and log data during and after startup of the plant, to follow trends through digital printouts of both measured and calculated variables, and to monitor and check instruments and equipment.
		The priority interrupt system can handle a number of separate interrupt sources in the order of their importance both with respect to each other and to the program in progress; for each interrupt line, the 330 has a unique response, so that no executive routine is required to locate the interrupt source.
	ed-thelen.org /comp-hist/BRL64-t.html (4081 words)

	Another W97M/Cartman.Poppy Infected Document
		The input Clk signal is for synchronous operation.
		The 7-bit output, ALUcontrol determines which operation is to be executed and the corresponding module to perform this task.
		The input Clk signal is again for synchronous operation and the Ena input signal si to enable the operation.
	www.engr.sjsu.edu /~cpham/SJSU/ee176f98/grp14.htm (1594 words)

	RS-232 Synchronous Serial PCMCIA Cards by Quatech
		Synchronous serial connectivity is an appropriate choice when rigorous security and intensive data integrity protocols are required for high-speed serial communication.
		It is the communication method of choice for a wide variety of military and commercial systems such as satellite monitoring, radar control, GPS systems, flight recorder data transfers, and HF (High Frequency) e-mail systems to name a few.
		Quatech's single port RS-232 synchronous serial PCMCIA card supports asynchronous data formats as well as byte-oriented synchronous protocols such as BiSync, and bit-oriented synchronous protocols such as HDLC and SDLC.
	www.quatech.com /catalog/rs232s_pcmcia.php (256 words)

	Point-to-Point Protocol
		The FCS field is calculated over all bits of the Address, Control, Protocol, Information and Padding fields, not including any start and stop bits (asynchronous) nor any bits (synchronous) or octets (asynchronous or synchronous) inserted for transparency.
		On asynchronous links, frames may be aborted by transmitting a "0" stop bit where a "1" bit is expected (framing error) or by transmitting a Control Escape octet followed immediately by a closing Flag Sequence.
		A "0" bit is inserted after all sequences of five contiguous "1" bits (including the last 5 bits of the FCS) to ensure that a Flag Sequence is not simulated.
	www2.rad.com /networks/2005/ppp_and_hdlc/ppp_util.htm (1657 words)

	BitKeeper use in classified environments
		Other systems claim to be distributed but all they really mean is that there is a local copy of some version of the data and to update that, roll it backwards or forwards, or perform any other revision control operation, there must be a network connection to a centralized server.
		It is easy to test if this is true by cloning a copy of a repository onto a laptop, unplug the laptop from the network, and run some tests against the repository.
		A pull operation is actually made up of several sub-operations.
	www.bitkeeper.com /usage/airgap/all.html (1313 words)

	Linux.com - Serial HOWTO: Other Serial Devices (not async EIA-232)
		In practice, an async signal is what the async serial port sends and receives which is a stream of bytes with each byte framed by a start and stop bit.
		Most of them are for use in synchronous communication which is seldom implemented in chips for PC's.
		This strips off the start/stop bits and puts the data bytes in packets resulting in synchronous operation over the phone line.
	www.linux.com /howtos/Serial-HOWTO-22.shtml (1700 words)

	Gems from e-BIT: Living with the Garbage Collector
		So, for the IBM Java SDK, GC is a purely synchronous operation and only occurs when a memory allocation fault occurs.
		GC is an expensive operation in terms of CPU usage and time.
		Mistakes made elsewhere in the code are often tripped over by the GC, as its normal operation is a thorough check on the state of a system when it runs.
	www-106.ibm.com /developerworks/java/library/j-jtctips/j-jtc0117b.html (1018 words)

	IDT Speeds Up Specialty SRAMs - Technology News by TechWeb
		Standard bidirectional devices provide 36-bit synchronous operation for multiple 32-bit processor systems such as voice compression.
		And triple-bus devices support half-duplex operation on the processor side and full duplex at the other end.
		Most useful for Fibre Channel networking, the triple-bus devices also feature a loop-back function, which lets data bypass the FIFO I/O port and be sent directly from one memory array to the other.
	www.techweb.com /wire/story/TWB19991018S0016 (461 words)

	X-bit labs - Print version
		Athlon 64 X2 3800+ does support this technology, and its only peculiarity is the synchronous frequency and voltage reduction of the two cores in case the CPU is not loaded heavily.
		This is another illustrative evidence of high efficiency of x86-64 architecture: the 32-bit applications performed in the compatibility mode in 64-bit operating system work at the same speed as in their authentic 32-bit environment.
		As for the drawbacks of the newcomer, we have to say that for some reason we were not at all impressed with its overclocking potential, as it only reached 2.4GHz.
	www.xbitlabs.com /articles/cpu/print/athlon64-x2-3800.html (4116 words)

	A Synchronous Binary Counter
		A Basic Digital Counter), we noted the need to have all flip-flops in a counter to operate in unison with each other, so that all bits in the ouput count would change state at the same time.
		When we started our look into counters, we noted a lot of applications involving numeric displays: clocks, ovens, microwave ovens, VCRs, etc. These applications require a decimal count in most cases, and a count from 0 to 5 for some digits in a clock display.
		Obviously there is a way, since digital clocks and watches do exist and do work.
	www.play-hookey.com /digital/synchronous_counter.html (566 words)

	RS-422/485 Synchronous Serial PCMCIA Cards by Quatech
		Quatech's single port RS-422/485 synchronous serial PCMCIA card supports asynchronous data formats as well as byte-oriented synchronous protocols such as BiSync, and bit-oriented synchronous protocols such as HDLC and SDLC.
		The card's robust design provides 1024-byte transmit and receive FIFOs that support interrupt-driven communication with data rates up to 2.45 Mbps.
		The MPAP-200/300 is currently being redesigned for 3.3V operation.
	www.quatech.com /catalog/rs422s_pcmcia.php (274 words)

	A Roadmap to Z-World's Rabbit-Based Sample Programs
		Outputs HOUT1 and HOUT2 are configured to demonstrate tristate operation to toggle the LEDs on the Demonstration Board.
		Output HOUT3 is configured as a sinking output to toggle an LED on the Demonstration Board.
		This is because certain byte patterns along with the stop bit will appear to generate the correct parity for the UART.
	www.rabbitsemiconductor.com /documentation/SamplesRoadmap/roadmap.htm (6327 words)

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