Block-transfer instruction

Block-transfer instruction - Factbites
Where results make sense
About us | Why use us? | Reviews | PR | Contact us

Topic: Block-transfer instruction

Note: these results are not from the primary (high quality) database.

In the News (Fri 25 Dec 09)

Northern Trust

Marvin Harrison

Peter Chernin

Gary Locke

Match Play

Penelope Cruz

Mickey Rourke

AR Rahman

Danny Boyle

Hugh Jackman

	Patent 4142233: Refreshing system for dynamic memory
		This instruction is a block transfer instruction for transferring memory contents from memory area A to memory area B by the direct memory access (DMA) mode transfer.
		In stage II, CPU is executing the block transfer instruction and the refreshing operation progresses.
		One form of the format of the instruction used for refreshing the memory contents of the dynamic memory 12 is shown in FIG.
	www.freepatentsonline.com /4142233.html

	Patent 5267350: Method for fetching plural instructions using single fetch request in accordance with empty state of instruction buffers and setting of flag latches
		As the instruction is fetched and decoded and the decoded instruction is fed to the instruction processor, a flag latch is so set as to correspond to the instruction buffer fetched and a report is given to indicate that the corresponding instruction buffer is in an empty state.
		An instruction fetch control method is generally arranged so as to have a plurality of instruction buffers, issue an instruction read request to a memory when a part of the instruction buffers becomes in an empty state and store a fetched instruction in the instruction buffer in an empty state.
		The instruction fetch control method as claimed in claim 1, wherein the method further comprises resetting the flag latch by using the response signal issued by the memory after the first instruction read request is issued and used for fetching the fetched first and second instructions from the memory.
	www.freepatentsonline.com /5267350.html

	Chapter 8. Block Transfers, Mesa Process Mechanism
		As with the other Block Transfer instructions, if the source and destination blocks overlap, and the destination address is less than the source address, bytes must be transferred on at a time from the source into the overlap area.
		The block transfer instruction move multiword structures from a source address to a destination address, or they com pare two multiword structures for equality.
		The arguments to Bit Block Transfer is a short pointer to a record containing the source and the destination bit addresses and bits per line, the width and height (in bits) of the rectangle to be operated on, and a word of flags that indicate the operation to be performed.
	www.digibarn.com /friends/alanfreier/princops/08xBlockTransfers.html

	Patent 5414821: Method of and apparatus for rapidly loading addressing environment by checking and loading multiple registers using a specialized instruction
		The instruction is decoded through the use of a microcode controller by instruction decode 123, and the operand address is computed by address generator 126 from the data received via path 131.
		Upon the request of instruction processor 14 to access a particular data element as either an instruction or operand, the directory of instruction cache 82 or operand cache 84, respectively, is queried to determine if the required data element is present within the associated cache resource.
		Instructions from instruction cache 82 are provided via path 106 to control section 104 for decoding via microcode controller and hardwired control logic.
	www.freepatentsonline.com /5414821.html

	Patent 4763251: Merge and copy bit block transfer implementation
		In the preferred embodiment, the memory is a bit addressable multi-dimensional array memory that includes a micro-processor and special circuitry to perform bit block transfers by accessing data using special circuitry that automatically decrements or increments the addresses.
		The accessing circuitry is further used to perform bit block transfers of data within the memory.
		A very useful function for bit mapped displays is the ability to move a rectangular block of pels from one place in the bit map to another place and logically combine the source rectangle with the destination rectangle.
	www.freepatentsonline.com /4763251.html

	pcetech.txt
		The operation defined by the instruction is performed using the memory location as one operand, and the effective address as the other.
		T can be set by the SET instruction, or by pushing a byte with bit 5 set and pulling it into P via PLP (in which case the instruction after PLP will be affected as if SET came before it).
		Bit 3 is set when a VRAM to SAT transfer has finished, which seems to always happen four lines after the last line in the active display period.
	cgfm2.emuviews.com /txt/pcetech.txt

	Your Personal PLC Tutor Site - Interactive Q & A - "Scaling at card versus in PLC; pros and cons"
		2) The PID instructions don't have to have 0-4095 as inputs for the PV.
		What I typically do is have a set of float registers assigned for scaling, and then use the FAL instruction to scale the entire input module's registers into floats in one shot.
		I know that in the Modicon PLC you have to use the raw analog signal as an input to the PID function block, but according to the AB manual you do not have to.
	www.plcs.net /dcforum/DCForumID1/1909.html

	CDC
		In addition there is a block transfer instruction for the high speed transfer of data.
		Data is transferred between the 1604 and IO (either a tape controller or the CDC 160) via 3 Input and 3 Output channels that operate concurrent with the main program.
		Program interrupt was used to synchronize the various IO transfers.
	research.microsoft.com /~gbell/craytalk/sld026.htm

	Block 4 Part 2 - Techniques of data transfer
		Interrupts are a data transfer method by which the device initiates the transfer, but the actual transfer is controlled by the processor.
		Such instructions are commonly used to allow programs access to device drivers without the program having to know the exact location of these drivers.
		Polling is a transfer technique which is initiated by the processor but controlled by the device.
	www.users.globalnet.co.uk /~kchilds/bl4part2.htm

	Your Personal PLC Tutor Site - Interactive Q & A - "Block transfer Write/read, PLC-5 (Ab)"
		These instruction transfer a block of data (up to 64 words) from the PLC to a module (BTW) or from the module to the PLC (BTR).
		Those instructions are the Block Transfer Write (BTW) and Block Transfer Read (BTR).
		The data registers contain the data that is to be transferred in one block.
	www.plcs.net /dcforum/DCForumID1/2250.html

	Citations: Hierarchical Memory with Block Transfer - Aggarwal, Chandra, Snir (ResearchIndex)
		added to the standard RAM special block transfer instructions of the form copy [a 1 : b 1 ] into [a 2 : b 2 ] This is valid so long as the two intervals of consecutive registers are disjoint and have the same size m.
		The notions of block transfer and hierarchy are developed further in a parallel model in which memory consists of a tree of modules, where computation takes place at the leaves [6] I O complexity models start with a single disk and CPU with block....
		Like HMM, it has a cost function f(z) but additionally it simulates the effect of block transfer by allowing the d 1 locations z, z to be accessed for cost f(z) d.
	citeseer.lcs.mit.edu /context/55013/0

	3Q97.html
		The RISC core has special instructions for these accelerate units: start execute instruction, wait for finish instruction and block data transfer instruction for the dedicated memories.
		This logic block incorporates support for digit-serial DSP architectures on a digit wide basis, without diminishing the support for random and control logic applications.
		The key to the suitability of the FPGA for these applications is the fact that each of its basic blocks is capable of processing a digit-size of up to 4-bits.
	www.ece.umn.edu /groups/ddp/dig_ser/3Q97.html

	Unisys History Newsletter v4n2
		The instruction set was expanded to add floating-point arithmetic, binary-to-decimal and decimal-to-binary conversions, and a block transfer instruction for movement of up to 64 words at a time.
		Type III instructions were made up of a 6-bit function code, a 6-bit minor function code, and a 6-bit data field.
		In Type II instructions, the high-order five bits for the address were always taken from the IAR.
	www.cc.gatech.edu /gvu/people/randy.carpenter/folklore/v4n2.html

	Block-transfer instruction - Wikipedia, the free encyclopedia
		On the PDP-10 the BLT (Block Transfer) instruction copies words from memory to memory.
		The left half of the selected AC specifies the first source address.
	en.wikipedia.org /wiki/Block-transfer_instruction

	Modbus Community site powered by Control.com
		I suggest you should have sequential or alternating block transfer instruction initiated to the RIO at a time.
		> You had not mentioned how many block transfer instruction you have.
		I think you are block transferring each individual racks (with 18 and 4 modules), so too much packets are involved on every block transfer message.
	modbus.control.com /user/addPostingForm?pid=1026200808

	53c7,8xx.h
		/ #define DBC_REG 0x24 / * For Block Move Instructions, DBC is a 24 bit quantity representing * the number of bytes to transfer.
		* For Transfer Control Instructions, DBC is bit fielded as follows : / / Bits 20 - 23 should be clear */ #define DBC_TCI_TRUE (1
		Instructions * write their high 8 bits into the DCMD register, the low 24 bits into * the DBC register.
	www.sunsite.org.uk /sites/tsx-11.mit.edu/pub/linux/ALPHA/scsi/ncr53c810/OLD/src.rel11+.1.2.13/53c7,8xx.h

	jargon, node: block transfer computations
		(The Z80's LDIR instruction, "Computed Block Transfer with increment", may also be relevant)
		block transfer computations /n./ [from the television series "Dr. Who"] Computations so fiendishly subtle and complex that they could not be performed by machines.
		Used to refer to any task that should be expressible as an algorithm in theory, but isn't.
	www.jargon.net /jargonfile/b/blocktransfercomputations.html

	B
		The jargon usage has outlasted the PDP-10 BLock Transfer instruction from which BLT derives; nowadays, the assembler mnemonic BLT almost always means `Branch if Less Than zero'.
		Various programs exist for rendering text strings into block, bloob, and pseudo-script fonts in cells between four and six character cells on a side; this is smaller than the letters generated by older banner (sense 2) programs.
		These are sometimes used to render one's name in a sig block, and are critically referred to as `BUAF's.
	www.th-soft.com /zzJargon/B.htm

	Inter-Institutional Block Transfer Agreements, 2004-05
		Transfer credits may be used only as electives for the B.A. in Adult Education.
		Minimum 63% average on diploma required to receive block credit.
		B.S.W. 6 units discretionary & university transfer credit.
	www.bccat.bc.ca /otg/block/bloc0405.htm

	JViewport (Java 2 Platform SE v1.4.2)
		The term "blit" is the pronounced version of the PDP-10 BLT (BLock Transfer) instruction, which copied a block of bits.
	java.sun.com /j2se/1.4/docs/api/javax/swing/JViewport.html

	Lecture 13: Blits and Double-Buffering
		This instruction was capable of copying some number of data bytes from one memory address range to another, and the modern meaning of blit is essentially unchanged: to blit is to copy a chunk of bytes from one memory address range to another -- memcpy if you will.
		A video card is a specialized piece of hardware that is able to communicate with the monitor and give it the "instructions" necessary to enable the monitor to determine which color to use for each pixel.
		A better solution is to provide the video card with a dedicated block of memory -- either system memory or separate memory on the card itself.
	www.digipen.edu /~mgrove/CS180/Lecture13.htm

	C073 Block Transfer Controller
		4) A1 24 15 16 This instruction starts the Block Transfer at the TSCC.
		For these tests the Block Transfer Con- troller is not used, a CAMAC kluge controller is used in its place.
		RALL: Receive All Block Transfers - When RALL is false, the BTR is in selective listener mode.
	www-bd.fnal.gov /controls/camac_modules/c073.htm

	BLT - Ursine
		The jargon usage has outlasted the PDP-10 bl ock t ransfer instruction from which BLT derives; nowadays, the assembler mnemonic BLT almost always means “ b ranch if l ess t han zero”.
		This page was last modified 16:55, 11 Mar 2005.
	ursine.dyndns.org /BLT

	BitBlt
		The name BitBlt is derived from a powerful bit-boundary block transfer instruction of that name found on one of the first machines to support Smalltalk, the Xerox Alto.
		Instances of class BitBlt (Block Transfer) describe a single graphical operation (often copy operations)
		Operations on objects are normally described as methods, not by instances of a class.
	minnow.cc.gatech.edu /squeak/189

	lecture17.txt
		Example: mov (sp)+, 10 or a block transfer instruction with source and destination overlapping each other; ----------------------------------------------------------------------------- Topic 1: how does MMU find a page table entry.
		The address is first feed to cache or instruction prefetch buffer, if it is there, done; *3.
		retry the instruction that was not finished due to the page fault; ----------------------------------------------------------------------------- Structure of a page table entry: valid bit, R/W/E permission bits (3 bits), clean/dirty bit, reference bit; the rest: used for physical page number; Structure of a TLB entry: Process ID + virtual page number, and the above page table entry.
	www.cs.wisc.edu /~cao/cs537/lecture17.txt

	RSLogix Forums - PLC 5 Block Transfer
		I have never used or had any training with Block Transfers or with PLC 5.
		The PLC program will then have a data file associated with a Block Transfer to that same Rack, Group, and Slot number.
		The data file in the Block Xfer will then have a 1 to 1 correspondence with the PV block.
	www.software.rockwell.com /forum/rslogix/messageview.cfm?catid=12&threadid=4972

	Application Note Technote: Block Transfer to 1746-NI4 Using ladder logic
		This example uses the Continuous Read Block Transfer to read back the incomming Analog values from the 1746-NI4 as fast as possible.
		A18004 - Block Transfer to 1746-NI4 Using ladder logic
		Note that certain jurisdictions do not countenance the exclusion of implied warranties; thus, this disclaimer may not apply to you.
	domino.automation.rockwell.com /applications/kb/RAKB.nsf/0/2C37AE4F4AB0237585256AFB0067EE96?OpenDocument

	The Amber Operating System - May 1984
		The Block Transfer instruction was included in the DEC PDP-10 architecture for doing this job.
		A kernel call can usually be done by a hardware trap instruction and is thus easy to get at.
		Code inside the kernel is shared by all users, which subroutines may not be, etc. However, the section on dynamic linking will show that subroutines need not be inside to kernel to be easy to use, and goes into more depth on the problems of putting too many functions in the kernel.
	www.mit.edu /%7Ecbf/thesis.htm

	US06820191-20041116.html
		An apparatus for executing block data transfer instruction inside a processor after receiving decode information containing N bits, the apparatus comprising:
		Apparatus and method for executing an instruction with a register bit mask for transferring data between a plurality of registers and memory inside a processor
	www.uspto.gov /web/patents/patog/week46/OG/html/1288-3/US06820191-20041116.html

Try your search on: Qwika (all wikis)

Topic: Block-transfer instruction

Ads by Google

Related Topics

In the News (Fri 25 Dec 09)