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Topic: Boundary Scan

	Boundary scan - Wikipedia, the free encyclopedia
		Boundary scan is a method for testing interconnects (thin wire lines) on printed circuit boards.
		The Joint Test Action Group (JTAG) developed a specification for boundary scan testing that was standardized in 1990 as the IEEE Std.
		The boundary scan architecture provides a means to test interconnects without using physical test probes.
	en.wikipedia.org /wiki/Boundary_Scan (246 words)

	Acculogic: Boundary Scan Home Page
		Boundary Scan, formally known as IEEE/ANSI 1149.1_1190 is a standard which facilitates testing, device programming and debugging at the semiconductor, board and system levels.
		For boundary scan testing, signal pins of compliant semiconductor devices are typically connected to cells in a parallel-in, parallel-out shift register.
		Implementing the boundary scan (JTAG) port has become a standard approach within the industry to programe most PLDs, CPLDs, etc., and suppliers of these devices are loyal to a policy of supporting the IEEE 1149.1 protocol.
	www.acculogic.com /Products/BoundaryScanHome.htm (943 words)

	JTAG Boundary Scan Basics White paper (Site not responding. Last check: 2007-10-11)
		Boundary scan is a methodology allowing complete controllability and observability of the boundary pins of a JTAG compatible device via software control.
		During this instruction, the boundary scan cells associated with outputs are preloaded with test patterns to test downstream devices.
		During this instruction, the boundary scan register can be accessed via a data scan operation, to take a sample of the functional data entering and leaving the device.
	www.engr.udayton.edu /faculty/jloomis/ece446/notes/jtag/jtag1.html (1137 words)

	APG Test Consultants, Inc.
		Boundary scan, when developed correctly, is the best solution for limited access testing and will provide fast, above average test coverage and diagnostic resolution.
		Boundary scan implemented improperly could result in total loss of test coverage on inaccessible nodes, in addition to potentially losing coverage on accessible nodes (because Boundary Scan disabling schemes fail).
		Boundary Scan is normally treated as a check the box item, an unimportant option not related to device operation.
	www.apgtest.com /scan_reasons.html (1736 words)

	Tech Tips Boundary Scan/JTAG Getting Started (Site not responding. Last check: 2007-10-11)
		Boundary Scan testing is used to identify faulty board-level connections, such as unconnected or shorted pins.
		Boundary Scan tests allow designers to quickly identify manufacturing or layout problems, which could otherwise be nearly impossible to isolate, especially with high-count ball-grid packages.
		Boundary Scan test vectors are typically derived from BSDL files, so if boundary scan tests are going to be performed on a configured Xilinx device, the BSDL file must be modified to reflect the device's configured Boundary Scan behavior.
	www.xilinx.com /xlnx/xil_tt_gettingstarted.jsp?sProduct=JTAG (1623 words)

	Boundary Scan Testing (Site not responding. Last check: 2007-10-11)
		The Boundary Scan Register and other test features of the device are accessed through a standard interface: the JTAG Test Access Port (TAP).
		The crux of the IEEE 1149.1 is a standard testability bus that implements boundary scan, which is a special type of scan path that consists of a series of test cells added at every I/O pin on a device (but not the TAP pins).
		Scan cells for all device pins connect to form a chain around the core logic, as Figure 2.12 shows.
	www.bolton.ac.uk /mind/corep/bst/bst-intro.html (5606 words)

	Test & Measurement World - Extend the frontiers of boundary-scan test - 2/1/2001 - Test & Measurement World - CA187304 (Site not responding. Last check: 2007-10-11)
		Nonetheless, to be of value, boundary scan must be integral to a product’s design strategy; it can’t be applied as a test afterthought.
		The rationale was that by designing every device with boundary scan, the engineers could use a VIT strategy to detect 100% of the pin short and open faults that might occur on the board, and designers could test prototype boards and have them repaired quickly to eliminate any structural faults.
		Although 1149.1 specifies the rules for boundary scan at the board level only, you can extend the advantages of boundary scan to system-level tests of multiple boards connected to a common backplane, whether you’re using a VIT or VCCT approach.
	www.reed-electronics.com /tmworld/article/CA187304.html (2393 words)

	Method and apparatus for universal programmable boundary scan driver/sensor circuit - Patent 5726999
		a boundary scan test access port circuit coupled to control receipt of the single data stream from the test data input pin to the circuit cells and delivery of the single data stream from the circuit cells to the test data output pin.
		The boundary scan driver/sensor integrated circuit of claim 10, further comprising a bypass register coupled to the test data input pin and the test data output port circuit, and operable to selectively pass data from the test data input pin to the test data output port circuit, bypassing the circuit cell serial scan chain.
		In this way, a Boundary Scan Driver/Sensor which is not to be used in the current JTAG operation may be bypassed, and the data coming in is shifted through register 37 and out onto the TDO pin for use by devices further along in the JTAG chain.
	www.freepatentsonline.com /5726999.html (4320 words)

	Articles - Scan (Site not responding. Last check: 2007-10-11)
		In data processing, image scanning is to optically analyze a two or three dimensional image and digitally encode it (digitize it) for storage in a computer file.
		Scanning is a term for the medical technique for body imaging.
		Scanning is the term for the lowest-level work of a software compiler, putting together the individual characters of the text of a computer program to form lexemes.
	www.mildhome.com /articles/Scanning (498 words)

	2 Boundary-Scan Architecture (Site not responding. Last check: 2007-10-11)
		The scan cells allow the state of the system pin to be controlled and observed.
		The design of the input and output scan cell is shown in Figure 2.5 and Figure 2.6 respectively.
		The scan cells receive mode signals from an instruction decoder (discussed in Chapter 3) and depending on the mode signals the scan cells choose either its parallel data or serial data.
	www.ececs.uc.edu /~ddel/theses/prasad/cover/node5.html (2164 words)

	Untitled (Site not responding. Last check: 2007-10-11)
		The boundary scan control circuitry allows us to scan in a test vector, present it to the circuit with a variable delay from the start of one of the four clock phases, and capture the outputs after a variable delay from one start of one of the clock phases.
		The boundary scan control circuitry allows to scan in a test vector, present it to the circuit with a variable delay from the start of one of the four clock phases, and capture the outputs after a variable delay from one start of one of the clock phases.
		In order to test the boundary scan scheme employed in the instruction decoder and data path slice chips, a small test chip was developed.
	inp.cie.rpi.edu /research/mcdonald/frisc/reports/fall93/f93.html (8347 words)

	conXscan - Boundary Scan for the Masses! (Site not responding. Last check: 2007-10-11)
		has developed a robust boundary scan solution tailored for companies either considering the benefits of boundary scan for the first time or looking to improve their existing boundary scan tools.
		Boundary scan is a powerful tool for enhancing maneuverability and streamlining test procedures, particularly for densely populated PCBs with BGAs.
		Aurora Logic provides the power of boundary scan in a concise, simplified interface while delivering all the tools expected from a comprehensive production test package.
	www.conxscan.com (143 words)

	( ESNUG 300 Item 3 ) ---------------------------------------------- [10/7/98]
		If you intend to use substantial amount of scan or other DFT logic, you may want to consider using the Fault Simulators in the DFT environment.
		Many of the tools insert BIST logic at the RTL level (unlike scan tools which usually operate at the gate-level or during the synthesis process).
		Boundary scan tools ------------------- These are often sold in conjunction with scan tools or BIST tools.
	www.deepchip.com /items/0300-03.html (1660 words)

	Connect - ASSET InterTech
		Multiple scan paths on a design is sometimes unavoidable even though a single scan path would make it simpler to generate boundary-scan tests and provide better test coverage.
		Boundary scan test systems like ScanWorks treat this situation in much the same way that they treat a single board with multiple scan paths.
		Each scan path described in a design is assigned a set of TAP signals that are identified by a channel (pod) number and a TAP number.
	www.asset-intertech.com /connect/2004Q1/observations.htm (2030 words)

	Amazon.com: The Boundary-Scan Handbook: Books (Site not responding. Last check: 2007-10-11)
		At the device level, the boundary scan elements contribute nothing to the functionality of the core logic.
		In fact, the boundary scan path is independent of the function of the device.
		On board the four; boundary scan devices are connected from one to the next in a serial format.
	www.amazon.com /exec/obidos/tg/detail/-/1402074964?v=glance (1364 words)

	Access the World of JTAG and Boundary Scan (IEEE 1149.1) Test Solutions
		JTAG, or as it is known by its official name, IEEE 1149.1 boundary scan, is your answer.
		In addition to cost savings from not requiring fixtures, boundary scan tests can be executed on a low-cost PC platform.
		Boundary scan gives you the power to create these benefits and more.
	www.asset-intertech.com /access_world_of_benefits.html (229 words)

	Boundary Scan Testing; Joint Test Action Group - JTAG; IEEE 1149.1
		Under normal operating conditions, the boundary cells simply let the input/output signals pass through them, into and out of the I/O pins.
		, however, these boundary cells become 'active' for use in the direct capture or control of the signals going into and out of the I/O circuitries of the device, circumventing the device's normal input and output connections.
		The boundary cells basically consist of multiplexed shift-registers that are located around the chip's periphery (hence the name 'boundary' cell).
	www.semiconfareast.com /jtag.htm (772 words)

	A Brief Introduction to JTAG
		It carries the sampled values from the boundary scan chain (or other JTAG registers) and propagates them to the next chip in the serial test circuit.
		EXTEST: With this command the boundary scan register (BSR) is connected between the TDI and the TDO signals.
		INTEST: With this command the boundary scan register (BSR) is connected between the TDI and the TDO signals.
	www.inaccessnetworks.com /projects/ianjtag/jtag-intro/jtag-intro.html (1872 words)

	Renowned boundary-scan seminar series kicking off for fall 2004 (Site not responding. Last check: 2007-10-11)
		Once you have the file saved to your computer hard drive, it is timeto scan it for viruses using...
		Wayne County might be using optical scan equipment to tabulate electionresults in...
		"It is staggering, frankly, to conceive of the scan of a...
	www.itnowonline.com /235/9025.htm (596 words)

	Design methodology for the S/390 Parallel Enterprise Server G4 microprocessors
		Initial values for the scan process are passed to the latch primitives through generics.
		This type of assertion must be used whenever there is a circuit that requires a condition for determinant function derived from primary inputs and is a thoroughly safe mechanism for expressing logical "don't-cares"; that is, all other conditions not covered by the assertion belong explicitly to the don't-care set.
		Following initial placement, which is done without regard to the scan-chain connectivity, the scan chains are reordered on the basis of latch placement to minimize the total scan-chain length.
	www.research.ibm.com /journal/rd/414/shepard.html (14877 words)

	Download JTAG software demo, training videos and technical articles on boundary scan test.
		Remember Universal Scan only scans the parts at a 10Hz rate, so you are not going to see a 200 Hz clock...what you will see is a blinking pin (virtual LED), which tells you there is activity at that pin.
		The benefits of boundary scan are fully understood and adopted by these industry segments.
		Boundary scan tools available for circuit card assembly fault-analysis are mature and well integrated into the test flow in these applications.
	www.ricreations.com /JTAG-Software-Downloads.htm (1249 words)

	Boundary Scan Schemes (Site not responding. Last check: 2007-10-11)
		Boundary Scan-Based Relay Wave Propagation Test of Arrays of Identical Structure...
		Using a single input to support multiple scan chains...
		Saddlepoint approximations and nonlinear boundary crossing probabilities of Mark...
	www.scienceoxygen.com /electrical/301.html (385 words)

	Universal Scan Adds SPI FLASH Programming to JTAG Test Tool Suite; Inexpensive Boundary Scan Test Software Programs ... (Site not responding. Last check: 2007-10-11)
		Universal Scan is a low level JTAG board and chip debug tool used by hardware and test engineers to view and manipulate circuit card signal activity via the JTAG port in real time while the circuit is running.
		Universal Scan Version 8 is available now at only $895 USD, the same affordable price that used to just include the boundary scan test functionality.
		Included for this price is Universal Scan boundary scan test and flash programming software, multi-vendor demo board with 9Vdc power supply, user manual and online training videos, USB security key, and free software upgrades for the first year.
	www.forbes.com /businesswire/feeds/businesswire/2005/07/28/businesswire20050728006083r1.html (775 words)

	Boundary Scan / JTAG systems
		We are very pleased with our purchase of a Corelis Boundary Scanning System as it has proven to be an invaluable tool in identifying faults in boards supplied by our Contract Manufacturers.
		We also act as main distributor and support centre for Corelis Inc, who are a market-leading US-based supplier of boundary scan hardware and software providing unparalleled performance and advanced features.
		Since Direct Insight is unique in addressing both embedded development and boundary scan test, we can help you to understand the issues.
	www.directinsight.co.uk /function/boundary-scan-jtag.html (412 words)

	Boundary Scan Test Software & JTAG Configuration (Site not responding. Last check: 2007-10-11)
		Boundary Scan begins with easy to use JTAG scan components.
		Boundary Scan test tools - Read how the Eclipse boundary scan family fits into your PCB scan test and FLASH programming strategy.
		Boundary Scan Test Development Environment is a complete solution for 1149.1 based testing, debug and in-system configuration of complex PCBs and Systems.
	www.intellitech.com (431 words)

	Boundary-Scan Tutorial
		All of this is controlled from a serial data path called the scan path or scan chain.
		The scan chain must work correctly prior to proceeding to other tests and in-system programming.
		Following a successful testing of the scan chain, the user can proceed to testing all the interconnects between the boundary-scan components.
	www.corelis.com /products/Boundary-Scan_Tutorial.htm (2675 words)

	Boundary-scan conversion (Site not responding. Last check: 2007-10-11)
		Boundary-Scan is a test technique standardized by the IEEE organization which is more and more used in the electronic community in order to be able to face the production test requirements both technically and financially speaking.
		Boundary Scan tests arise first in the early phases of the development of complex PCB and so is firstly used by design engineers in order to validate their designs.
		According to the fact that most of the manufacturing departments use In-Circuit test systems for their PC Boards production test, it is now important to be able to run on existing ICT testers (large investment already done) Boundary scan tests coming from testers used by the design peoples.
	www.aster-ingenierie.com /en-wildscan.htm (426 words)

	Business Wire: Vitalect Announces Web-Based Course on Boundary Scan Based on Award-Winning Tutorial by Industry Expert (Site not responding. Last check: 2007-10-11)
		The new online course, entitled Boundary Scan Tutorial, is intended for engineers involved in semiconductor and board level design and test, enabling them to obtain a broad understanding of boundary-scan technology and the very significant impact it has on the ability to produce high-quality boards.
		"In recent years, boundary scan technology has spread rapidly throughout the electronics industry, enabling manufactured boards to be tested to very high levels of quality assurance.
		"Consequently, this Boundary Scan Tutorial is the perfect example of the blending of industry expertise with web-based learning technology, to enable knowledge transfer quickly, economically and contextually to the engineers who need it.
	www.findarticles.com /cf_dls/m0EIN/2001_Oct_29/79502198/p1/article.jhtml (809 words)

	Early Capture For Boundary Scan Timing Measurements - Lofstrom (ResearchIndex)
		Introduction The IEEE 1149.1 Boundary Scan Test Standard [1,2] has found wide acceptance in the test community.
		Boundary scan is slowly gaining converts among the circuit designers that often control the introduction of new features into system design....
		Lofstrom, "Early Capture for Boundary Scan Timing Measurements", Proceedings of IEEE International Test Conference, October 1996.
	citeseer.ist.psu.edu /lofstrom96early.html (475 words)

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