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Topic: Branch delay slot

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	Branch delay slot - Wikipedia, the free encyclopedia
		Branch delay slots are found not only in several RISC architectures including MIPS, PA-RISC and SPARC but also in DSP architectures including µPD77230 and TMS320C3x.
		The branch delay slot is a side-effect of pipelined architectures due to the branch hazard, i.e.
		The number of branch delay slots in a particular pipeline implementation is dictated by the number of pipeline stages, the presence of register forwarding, what stage of the pipeline the branch conditions are computed, whether or not a branch target buffer (BTB) is used and many other factors.
	en.wikipedia.org /wiki/Branch_delay_slot (343 words)

	Branch predictor - Wikipedia, the free encyclopedia
		Branch predictors are crucial in today's modern, superscalar processors for achieving high performance.
		Branch prediction is not the same as branch target prediction.
		Branch target prediction attempts to guess the target of the branch or unconditional jump before it is computed from parsing the instruction itself.
	en.wikipedia.org /wiki/Branch_predictor (2614 words)

	Encyclopedia :: encyclopedia : Tom DeLay (Site not responding. Last check: 2007-11-01)
		DeLay was indicted in Austin, Texas on criminal charges of conspiracy to violate election laws in 2002 by a Travis County, Texas grand jury after having waived his rights under the statutes of limitations.
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	www.hallencyclopedia.com /Tom_DeLay (4857 words)

	Branch Prediction Schemes
		In a delayed branch, the execution cycle with a branch delay of length n is
		In (a) the delay slot is scheduled with an independent instruction from before the branch.
		In the code sequences for (b) and (c), the use of R1 in the branch condition prevents the ADD instruction (whose destination is R1) from being moved after the branch.
	www.cs.iastate.edu /~prabhu/Tutorial/PIPELINE/branchPred.html (665 words)

	[No title] (Site not responding. Last check: 2007-11-01)
		On machines that have instructions requiring delay slots (note Delay* Slots::.) or that have instructions whose output is not available for multiple cycles (note Function Units::.), the compiler phases that optimize these cases need to be able to move insns into one-instruction delay* slots.
		If an insn needs to be split for delay slot scheduling or insn scheduling, the insn is already known to be valid, which means that it must have been matched by some `define_insn' and, if `reload_completed' is non-zero, is known to satisfy the constraints of that `define_insn'.
		Delay slot scheduling differs from instruction scheduling in that determining whether an instruction needs a delay slot is dependent only on the type of instruction being generated, not on data flow between the instructions.
	www.cs.purdue.edu /homes/gomez/research/egcs-1.1b/info/gcc.info-20 (5157 words)

	3 Implementing Control Structures
		The branch delay slot arises because the PC is assigned the old value of nPC (before nPC is assigned the target of the branch).
		Every branching instruction can specify that the affect of the instruction in the branch delay slot is to be nullified (annulled in SPARC terminology) if the branch specified by the conditional branching instruction is not taken.
		When a branch instruction is in the delay slot of another branch instruction, the pair of branch instructions is called a ``delayed control-transfer couple''.
	www.cs.unm.edu /~maccabe/classes/341/labman/node3.html (1619 words)

	[No title]
		Currently DLXSIM models branches by assuming a single-cycle branch delay slot with branches resolved in the ID stage, which implies that no stalls are needed.
		Your project is to modify the code to simulate a machine without a branch delay slot; and instead handle branches by each of the following techniques: flushing, predicted-not-taken and dynamic branch prediction using a branch target buffer, depending on the command-line option used.
		Assume that branches continue to be resolved in the ID stage in your new branching models.
	www.ee.umd.edu /courses/enee446-2.S2004/project.html (1023 words)

	[No title] (Site not responding. Last check: 2007-11-01)
		Instead, the functions simulating the conditional branch instructions return a boolean that states whether the branch should be taken or not; performing the branch is the job of the C code.
		Since DLX branch instructions are delayed branches, they must take place after the execution of the instruction that follows the branch instruction itself.
		You act on this return value by adding a conditional goto in your C code after the instruction in the delay slot of the branch, this goto specifying the target of the conditional branch instruction.
	www.cs.mu.oz.au /313/2003/proj2.tty (1935 words)

	[No title]
		Independently of the outcome of the branch, the delay slot instuction is fetched and its execution begins.
		The annul bit in the branch instruction tells the hardware to nullify the effect of the delay slot instruction in the case that the branch is not taken.
		When the branch is not taken, the work done on the delay slot instruction is wasted but it doesn't cause incorrect results.
	www.cs.albany.edu /~sdc/csi504/Lect23 (622 words)

	[No title] (Site not responding. Last check: 2007-11-01)
		Branch delay slots Jump and branch instructions have a delay of one cycle while they fetch the instruction at the target address if the branch is taken.
		The instruction immediately after the jump or branch* is in the branch delay slot and is always executed, regardless of whether the conditional branch is taken or not!* A simple way to prevent branch and jump hazards is to put a NOP in the branch delay slot.
		Another way to use the branch delay slot is to replicate the instruction that is the target of the branch/jump into the load delay slot, provided no side effects occur if the branch falls through.
	www.cs.ualberta.ca /~macg/C429/Extras/spim.html (2468 words)

	Control flow
		Branches are always relative, the branch destination is added to the current location (a jump instruction is absolute).
		If the branch is taken, there is a delay between the time the branch instruction is executed and the execution resumes at the new location.
		The jump instruction is similar to a branch instruciton, except the instruction's operand points to the absolute address at which to resume execution.
	www.engr.uconn.edu /~jeffm/Classes/CSE240-Spring-2000/Lectures/lecture10/node3.html (321 words)

	Reduced instruction set computer - Wikipedia, the free encyclopedia
		A branch delay slot is an instruction space immediately following a jump or branch.
		The instruction in this space is executed whether or not the branch is taken (in other words the effect of the branch is delayed).
		Nowadays the branch delay slot is considered an unfortunate side effect of a particular strategy for implementing some RISC designs, and modern RISC designs generally do away with it (such as PowerPC, more recent versions of SPARC, and MIPS).
	en.wikipedia.org /wiki/RISC (4216 words)

	Larceny Note #6: Larceny on the SPARC
		The branch delay slot can be filled in the usual manner or it can be used to adjust the value of o7 if L0 is not at the call instruction.
		Currently, it fills branch delay slots using a simple algorithm: if the branch target is an instruction that can go in a delay slot, then insert the target instruction in the delay slot and increment the branch offset by 4.
		Certainly, in the case of a branch, the target is known to the processor well before the branch instruction is executed, hence the target instruction has probably been fetched already, and the memory system is available for the store.
	www.ccs.neu.edu /home/will/Larceny/notes/note6-sparc.html (2390 words)

	[No title]
		We chose to introduce one branch delay slot at the compiler level and designed the hardware to introduce the bubbles in the pipeline as necessary.
		Branch instruction Stage2 During the second stage, the branch will be resolved by the combinational circuit that tests the C, Z, N & V bits along with the “cond” field of the Branch instruction.
		Thus critical path delay = max(41, 44, 64, 29, 14) = 64 Practically, we verified the critical path delay to be 64.
	www-users.cs.umn.edu /~msang/projects/vespa.doc (2488 words)

	Branch Strategies in Pipelines (Site not responding. Last check: 2007-11-01)
		Branches are therefore a significant problem; particularly conditional branches because there are two possible outcomes, and we do not know which will occur.
		The idea is that a branch instruction does not cause an imediate branch, but is delayed by some number of cycles, depending on the length of the pipeline.
		The basic problem with conditional branches in pipelines is that they [usually] depend on the value of some condition code that has not yet been computed (because the instruction computing the value of the code is still in the pipeline).
	www.cs.swan.ac.uk /~csneal/HPM/branchstrat.html (3687 words)

	Data Hazards
		Deciding whether or not the branch is taken earlier in the pipeline.
		Branch delay can be reduced to 1 cycle.
		Note that the instruction(s) in the branch delay slot(s) after the branch are always executed.
	www.cs.umbc.edu /~plusquel/611/slides/chap3_4.html (734 words)

	Review of the Machine Cycle (Site not responding. Last check: 2007-11-01)
		The instruction that follows a jump instruction in memory is said to be in the branch delay slot.
		The instruction that follows a jump instruction in memory (in the branch delay slot) is always executed.
		Often the branch delay slot is filled with a no-op instruction.
	chortle.ccsu.ctstateu.edu /AssemblyTutorial/Chapter-17/ass17_2.html (401 words)

	[No title] (Site not responding. Last check: 2007-11-01)
		schedule the code to remove as many stalls as possible assuming a branch delay slot is available, and show the timing diagram for 1 iteration plus the first instruction of the next for your scheduled code.
		Assume branches are handled by flushing the pipeline until branches are determined in the EX stage.
		An optimizing compiler is able to schedule for both machines 1 instruction to remove any RAW hazard 80% of the time and the branch delay slot 60% of the time.
	www.nku.edu /~foxr/CSC462/hw4.doc (353 words)

	Untitled Document
		So, when a branch instruction is encountered, the hardware puts the instruction following the branch into the pipe and begins executing it, just as in predict-not-taken.
		However, unlike in predict-not-taken, we do not need to worry about whether the branch is taken or not, we do not need to clear the pipe because no matter whether the branch is taken or not, we know the instruction is safe to execute.
		When the program was compiled, the compiler looked at each branch instruction, and tried to find something that could be safely executed, whether we take the branch or not.
	www.cs.umd.edu /class/fall2001/cmsc411/projects/branches/delay.html (648 words)

	[No title] (Site not responding. Last check: 2007-11-01)
		This implies that 18/20 or 90% of backwards branches are taken, and that 48/80 or 60% of forwards branches are taken.
		The motivation for profiling is that an individual branch can have a strong probability of being taken or untaken, and the average over all branches leading to the rule of thumb is not a good predictor of the exceptional branches.
		With branch delay slots, it is not possible to restart on the basis of a single PC, because instructions in the pipe may not be sequentially related.
	www.cs.odu.edu /~keyes/cs665/lec6/lec6.html (1762 words)

	MIPS R32 Instructions
		If the contents of GPR rs are greater than or equal to zero (sign bit is 0), branch to the effective target address after the instruction in the delay slot is executed.
		If the contents of GPR rs are less than or equal to zero (sign bit is 1 or value is zero), branch to the effective target address after the instruction in the delay slot is executed.
		The remaining upper bits are the corresponding bits of the address of the instruction in the delay slot (not the branch itself).
	www.cs.uwm.edu /~cs215/TAL_instructions.html (3522 words)

	EE108B LAB3 FAQ
		The branch delay slot is reserved for an instruction that will be executed regardless of the direction of the branch (both conditional and unconditional types).
		No, the definition of branch instructions are not affected by the branch delay slot (it is the same as defined on P.146 in the text.
		However, the branch delay slot does affect what the link address should be.
	www.stanford.edu /class/ee108b/labs/restricted/lab3/lab3_faq.htm (1263 words)

	[No title]
		The effects of the delay slot in a conditional branch can be nullified for forward taken branches, or for untaken backward branches.
		Then it searches after the insn requiring delay slots or, in the case of a branch, for insns that are after the point at which the branch merges into the fallthrough code, if such a point exists.
		Use either a branch that annuls when the condition if true or invert the test with a branch that annuls when the condition is false.
	www.cs.cmu.edu /afs/cs.cmu.edu/project/amulet-4/jh6p/classes/studio/gcc-2.5.8/reorg.c (6215 words)

	Operating Systems Lecture Notes Lecture 11 MIPS TLB Structure
		EPC register: points to instruction that caused fault, unless faulting instruction was in branch delay slot.
		JR kt1; rfe instruction in branch delay slot.
		Branches to general exception handler (different from UTLB miss handler).
	www.cag.lcs.mit.edu /~rinard/osnotes/h11.html (2122 words)

	Control Hazards
		This is surprisingly effective since 85% of backward branches and 60% of forward branches are taken.
		This scheme is similar to predicting all branches as taken except that it uses information about the types of branches.
		It is not perfect since many branches are both taken and not taken in the course of execution.
	www.cs.umbc.edu /~plusquel/611/slides/chap3_5.html (1213 words)

	Completion
		If the branch had not yet received a shadow mapper, it is no longer considered to be stalled for a mapper.
		is used to remove the shadow mapper associated with the current branch and all later branches.
		is invoked to remove all instructions from the memory unit after the branch or delay slot in question.
	www.msu.edu /~vallamse/html/node81.html (429 words)

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