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Topic: Branch instruction

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	Branch predictor - Wikipedia, the free encyclopedia
		In computer architecture, a branch predictor is the part of a processor that determines whether a conditional branch in the instruction flow of a program is likely to be taken or not.
		Branch prediction is not the same as branch target prediction.
		Unlike the instruction cache, bimodal predictor entries typically do not have tags, and so a particular counter may be mapped to different branch instructions (this is called branch interference or branch aliasing), in which case it is likely to be less accurate.
	en.wikipedia.org /wiki/Branch_prediction (2226 words)

	Branch delay slot - Wikipedia, the free encyclopedia
		The branch delay slot is a side-effect of pipelined architectures due to the branch hazard, i.e.
		The number of branch delay slots in a particular pipeline implementation is dictated by the number of pipeline stages, the presence of register forwarding, what stage of the pipeline the branch conditions are computed, whether or not a branch target buffer (BTB) is used and many other factors.
		By using branch prediction techniques and speculative execution, many of these branch delay slots are efficiently utilitized, reducing the performance penalty incurred by these branch instructions.
	en.wikipedia.org /wiki/Branch_delay_slot (343 words)

	U.S. Patent: 5542109 - Address tracking and branch resolution in a processor with multiple execution pipelines and ...
		Branch pipeline 10 is adapted for processing simple branch instructions and generating target addresses, and may contain branch prediction logic in the early stages such as the D stage.
		Thus the branch resolver must supply two addresses: the recovery address of the instruction immediately after the branch instruction, which is either the target address or the sequential address, and the address of the branch instruction itself, which is used to update the branch prediction logic.
		This branch instruction address is generated by adder 64 and is also known as the update address 70, because the address of the branch instruction is sent to the branch prediction unit to locate the branch prediction entry corresponding to the branch instruction resolved by branch resolver 60.
	www.everypatent.com /comp/pat5542109.html (12537 words)

	U.S. Patent: 5051896 - Apparatus and method for nullifying delayed slot instructions in a pipelined computer system - ...
		The next instruction in the instruction pipeline may be nullified according to the preferred embodiment of the present invention by setting the nullify bit 507.
		When the branch condition is true, the delay slot instruction is executed and then the instruction at the target address is executed as shown in graph 111 for a negative displacement branch and in graph 113 for a positive displacement branch.
		With the nullify bit on, a backward conditional branch that is taken or a forward conditional branch that is not taken, being the tasks that are predicted to be frequent by the static branch prediction technique, cause the delay slot instruction to be executed.
	www.everypatent.com /comp/pat5051896.html (3843 words)

	Multi-instruction stream branch processing mechanism - Patent 4200927
		instruction selection means, responsive to said result signals from said execution unit in response to said branch instruction and said associated target buffer indicating means, for selecting the next sequential execution control information to be transferred to said execution unit.
		The branch status signals on line 116 indicating a particular kind of branch instruction being executed, will be logically combined with results from the ALU 103 on a line 117 to signal back to the IPPF 20 the results of data manipulations which determine the success, or not, of conditional branch instructions.
		If a second conditional branch instruction is decoded, and one of the Instruction Buffers 31, 32 or 33 is not active, a third instruction fetch for a third instruction stream may be initiated, and the same determination as to the success of the conditional branch instruction made.
	www.freepatentsonline.com /4200927.html (11691 words)

	System for reexecuting branch instruction without fetching by storing target instruction control information - Patent ...
		The target address of a branch instruction is stored in the index field of an associative memory, and control information obtained by decoding a target instruction of branch corresponding to the branch instruction is stored in the data field of the associative memory beforehand.
		When executing the branch instruction, the associative memory is accessed with the target address, and the control information of the corresponding entry is read out and is transferred to the instruction execute circuit, whereupon the instruction execute circuit starts executing the target instruction of branch instruction in succeession to the execution of the branch instruction.
		Meanwhile, the branch instruction.circle.1 is fetched from the memory 20 and decoded by the instruction decoder 21.
	www.freepatentsonline.com /4912635.html (7754 words)

	Branch prediction in the Pentium family (Site not responding. Last check: 2007-10-26)
		A branch instruction is the implementation of an if-then-else construct.
		The branch instruction is predicted to jump next time if in state 2 or 3, and to not jump when in state 0 or 1.
		The branch instruction is predicted to jump next time if the counter is in state 2 or 3, and to not jump if in state 0 or 1.
	x86.org /articles/branch/branchprediction.htm (1921 words)

	Unconditional Branch Instruction (Site not responding. Last check: 2007-10-26)
		he pseudocomputer has an unconditional branch instruction that always causes a branch.
		must be relatively close to the branch instruction, as is true with all branch instructions.
		The 32-bit address is computed using a 16 bit offset in the instruction and the current value of the PC.
	chortle.ccsu.ctstateu.edu /AssemblyTutorial/Chapter-24/ass24_3.html (103 words)

	Java Virtual Machine - Wikipedia, the free encyclopedia
		For easier distribution of large programs, multiple class files may be packaged together in a.jar file.
		This binary is then executed by the JVM runtime which carries out emulation of the JVM instruction set by interpreting it or by applying a just-in-time compiler (JIT) such as Sun's HotSpot.
		In fact, code verification makes the JVM different from a classic stack architecture whose efficient emulation with a JIT compiler is more complicated and typically carried out by a slower interpreter.
	en.wikipedia.org /wiki/Java_virtual_machine (790 words)

	Superscalar Branch Instruction Processor (ResearchIndex) (Site not responding. Last check: 2007-10-26)
		Abstract: In this paper we describe the design of the branch unit that has been implemented in some models of the recently announced IBM AS/400 1.
		The branch unit we describe is a modification of the unit originally designed for the experimental IBM ESA/370 2 SCISM processor.
		The main feature of branch unit is its capability to remove branch instructions from the instruction stream dynamically and pre-process them before the branches enter the pipeline.
	citeseer.ist.psu.edu /375843.html (393 words)

	Assembler Language Reference - bc (Branch Conditional) Instruction
		If the Absolute Address bit (AA) is 0, then the branch target address is computed by concatenating the 14-bit Branch Displacement (BD) and b'00', sign-extending this to 32 bits, and adding the result to the address of this branch instruction.
		The Branch Option field (BO) is used to combine different types of branches into a single instruction.
		Decrement the CTR; then branch if bits the decremented CTR is not 0 and the condition is True.
	www.nersc.gov /vendor_docs/ibm/asm/bc.htm (715 words)

	Instruction Prefetch (Site not responding. Last check: 2007-10-26)
		instruction prefetch A technique which attempts to minimise the time a processor spends waiting for instructions to be fetched
		Instruction prefetch means having first and second register for storing and providing a current PC while generating a next PC, United States
		In an instruction prefetch circuit, even when a branch instruction is prefetched, the circuit continues a prefetch operation until branching is
	www.instructionprefetch.info (799 words)

	C5510 DSK: one branch instruction costs 19 cycles ??!
		So, the cost of one branch instruction (no jump happens) is 19 cycles.
		From my test, I find the cycle cost of branch instruction is too much.
		between 7/6 cycles depending on branch being taken or not.
	www.dsprelated.com /showmessage/5301/1.php (1117 words)

	Moving Forth: Part 3
		When the JSR DEUX is executed, the address of the next instruction in the thread is pushed onto the Return Stack.
		In the case of the 6809, the address would be stored as the last two bytes of the three-byte JSR instruction.
		In this case, the relative offset must be computed and inserted into the branch instruction.
	www.zetetics.com /bj/papers/moving3.htm (6897 words)

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