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Topic: Branch misprediction

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	System for using a branch prediction unit to achieve serialization by forcing a branch misprediction to flush a ...
		The branch prediction unit is adapted to generate branch predictions for the branch instructions, direct the instruction fetch unit to retrieve the program instructions in an order corresponding to the branch predictions, and redirect the instruction fetch unit based on a branch misprediction.
		The goal of the branch prediction unit 30 is to identify and predict the outcome of branch instructions such that the instruction fetch unit 20 may retrieve the program instructions required by the execution engine 15 in advance.
		After a mispredicted branch instruction, instructions entered into the pipeline subsequent to the mispredicted branch instruction are flushed, and the pipeline is reloaded from the redirect instruction address stored in the branch resolution table 45.
	www.freepatentsonline.com /5954814.html (2611 words)

	Fast branch misprediction recovery method and system - Patent 6757816
		As a result of the misprediction, both the taken branch, represented by instructions 3 and 4, and the untaken branch, represented by instructions 1 and 2, are fetched.
		This is orthogonal to the case where several branches and their target reappear in the instruction windows, such as the case of a conditional branch within a loop, in which each new occurrence of a target resolves the last occurrence of the branch.
		Regardless of whether the branch was correctly predicted or not, and whether the detection of the alternative branch succeeded or not, the ABAT entry corresponding to the branch is always dismissed once the branch is committed.
	www.freepatentsonline.com /6757816.html (5696 words)

	SIMPLE SCALAR
		The effect of the size of the branch target buffer (BTB) on the branch misprediction rate is observed.
		Simulations are run on the three benchmarks specifying the branch predictor to be one of always taken, always untaken, bimodal predictor using a branch target buffer, or a 2-level adaptive predictor.
		The effect of the size of the BTB on the number of mispredicted branch directions is observed by running all the benchmarks varying the size of the BTB to be 256, 512, 1024, 2048, 4096 and 8192 bytes.
	www.ece.uci.edu /~pgontla/ss.html (1568 words)

	Dynamic Branch Prediction
		Branch prediction is used to overcome the fetch limitation imposed by control hazards in order to expose instruction-level parallelism (ILP), the key ingredient to pipelined and superscalar architectures that mask instruction execution latencies by exploiting (ILP).
		Branch prediction can be thought of as a sophisticated form of prefetch or a limited form of data prediction that attempts to predict the result of branch instructions so that a processor can speculatively fetch across basic-block boundaries.
		Uni-Direction Branches are branches with a probability to be taken between 0% and 10%, that means the branch is likely not to be taken, or between 90% and 100% which indicates a branch that is mostly taken.
	web.engr.oregonstate.edu /~benl/Projects/branch_pred (7437 words)

	Branch predictor - Wikipedia, the free encyclopedia
		A branch predictor regards computer architecture and is the part of a processor that determines whether a conditional branch in the instruction flow of a program is likely to be taken or not.
		Combined branch prediction uses three predictors in parallel: bimodal, gshare, and a bimodal-like predictor to pick which of bimodal or gshare to use on a branch-by-branch basis.
		If the hardware determined that the branch prediction state of a particular branch needed to be updated, it would rewrite the opcode with the semantically equivalent opcode that hinted the proper history.
	en.wikipedia.org /wiki/Branch_prediction (2616 words)

	Branch Prediction Research in the LAVA Lab (including hybrid predictors, speculative update, return address stack, and ...
		Improving branch prediction, although already a well-studied subject, remains critical because delivering very high branch-prediction rates is crucial to further performance gains in high-performance computing.
		For example, a single misprediction in the Alpha 21264 results in a minimum of 7 wasted cycles; in the Pentium 4, in a minimum of 17 wasted cycles.
		Not only do some branches in a program benefit from global history while others benefit from local history—a well known fact that suggests use of a hybrid predictor—but in fact individual branches vary between benefiting from global history and benefiting from local history.
	lava.cs.virginia.edu /bpred.html (819 words)

	Value Prediction
		In a typical processor, control speculation is a crucial tool that allows branch prediction both for the direction of a branch and the target of a branch.
		Misprediction: IR is not speculative, so it never needs to pay a misprediction penalty; whereas VP will incur such penalties.
		IR on the other hand will detect branch misprediction earlier (when it reuses instructions) and, even when misprediction cannot be avoided, IR will be caching the work done because of the misprediction for later reuse.
	www.cs.cmu.edu /~acw/15740/valuepred.html (1095 words)

	[No title] (Site not responding. Last check: 2007-11-05)
		From our analysis, the majority of exceptions are caused by branch misprediction so that when there is an exception happens, we will roll back to the previous branch and self-regulate the misprediction and fetch and issue instructions from the correct branch path.
		This exception is generated because of the misprediction at the branch instruction of (x!=0), and the best way to handle this exception is to take another branch and fetch and issue the instructions from another branch.
		If the bit is 1, the branch direction has been tentatively executed and exception happens during the tentative execution of this direction; otherwise, if the bit is 0, the direction can either be safe and correct or the direction hasn’t been tried to execute.
	www.crhc.uiuc.edu /~wngu/412project.doc (3305 words)

	final-paper
		The prediction of a conditional branch is based on the branch's own history and the pattern history bits in the global pattern history table entry indexed by the content of the branch's history register.
		The basic principle of the skewed branch predictor is to use several branch-predictor banks, but to index them by different and independent hashing functions computed from the same vector V of information (e.g., branch address and global history).
		It has also been shown that branch interference (also be called aliasing) is a major contributor to the number of branch misprediction by two-level predictor.
	www.eecis.udel.edu /~wzhou/course/cis662/paper.html (2652 words)

	2
		Consider a BTB that is correctly predicting the backward branch at the bottom of a loop; eventually that loop is going to terminate, and when it does, that branch will be mispredicted.
		Branch µops are tagged (in the in-order pipeline) with their fall-through address and the destination that was predicted for them.
		In that case the proper branch destination is provided to the BTB which restarts the whole pipeline from the new target address.
	www.mcs.drexel.edu /~gjchen/CS570reportF.htm (4282 words)

	PentOpt chapter 22
		The consequence of this flaw is, that a branch instruction which falls through most of the time will have up to three times as many mispredictions as a branch instruction which is taken most of the time.
		A branch instruction is predicted to be taken when the corresponding counter is in state 2 or 3, and to fall through when in state 0 or 1.
		The branch prediction is not reliable in tiny loops where the pattern recognition mechanism doesn't have time to update its data before the next branch is met.
	asdf.org /~fatphil/x86/pentopt/22.html (6852 words)

	Irisa : thèse proposée pour la rentrée 2001 (Site not responding. Last check: 2007-11-05)
		The penalty paid on each branch misprediction (either conditional or indirect) is huge and will continue to grow for next generation processors as they will feature more instruction level parallelism.
		It should also be noted that when complexifying the branch predictor results in an increase of its crossing latency, the extra accuracy may be counterbalanced by extra bubbles in pipeline front-end.
		In [1], pipelined multiple block ahead branch prediction, we proposed to predict fetch addresses using information available 2 or more cycles ahead the fetch cycles.
	www.irisa.fr /theses2001/caps2.htm (496 words)

	Smashing performance with OProfile
		But branch prediction is not always correct, and some branches are hard to predict.
		to not always be equal to 1, and hence branch misprediction occurs in the parent thread.
		by the parent thread causes branch misprediction in the clone thread.
	www.ibm.com /developerworks/linux/library/l-oprof.html (1993 words)

	Incorporating Predicate Information Into Branch Predictors
		This can cause what we call misprediction migration, where the poorly predictable pattern of a hard-to-predict branch that was eliminated due to predication is merely migrated to a region branch.
		The goal of this predictor is to correctly predict the region branches that are on the false path as not-taken.
		Region branches only benefit from these two branch prediction architectures if they are scheduled far enough apart from their predicate definitions.
	www-cse.ucsd.edu /~calder/abstracts/EPIC-01-PBP.html (794 words)

	Title page for ETD etd-05192006-150506
		Conventional superscalar processors recover from a mispredicted branch by squashing all instructions after the branch.
		When a misprediction is detected, first, the branch's correct control-dependent instructions are fetched from the conventional instruction cache as usual.
		The results include (i) breakdowns of retired dynamic instructions into different categories, based on their control and data dependences with respect to prior mispredicted branches, (ii) contributions of individual recovery traces to total CIDI instruction savings, and (iii) hit ratios of finite recovery trace caches.
	www.lib.ncsu.edu /theses/available/etd-05192006-150506 (396 words)

	[No title]
		If data hazard exists, that is to say, the branch condition or the branch target depends on the result of previous instructions which are still being executed in the pipeline, it may not be possible to resolve the branch in the ID stage.
		Branch Target Buffer Although branch predictors are able to accurately predict the direction of branch instructions, target addresses are still unknown until ID or EX stage.
		Although indirect branches are not as common as return instructions, they do affect the overall performance of the branch prediction, especially when their frequent occurrence in object-oriented languages becomes a serious issue.
	www.eecs.umich.edu /~hongtaoz/docs/470ProjRpt.DOC (5917 words)

	Ace's Hardware (Site not responding. Last check: 2007-11-05)
		To test the branch prediction further, we used the benchmark "Queens." Queens is a very well known problem where you have to place n chess queens on an n x n board.
		Damage control is necessary for the "Sledgehammer blows" that branch misprediction is delivering to the performance of the Pentium 4.
		The hint instructions are useful if (1) there are some branches in which the pattern does not converge well, but some degree of bias does nevertheless exist, or (2) there are so many branches that the CPU is running out of branch predictor resources.
	www.aceshardware.com /Spades/read.php?article_id=25000193 (581 words)

	Real World Technologies - What's Up With Willamette? (Part 2)
		When it encounters a conditional branch, the control unit has to predict which way program flow is likely to go and it continues to assemble the trace segment accordingly.
		Later on, in execute mode, the branch's uop is executed and the actual branch condition resolved.
		Willamette has about a twenty-cycle branch misprediction penalty even when the alternative path trace segment is present in the trace cache, but most of this is due to the stretched out execution pipeline.
	www.realworldtech.com /page.cfm?ArticleID=RWT040400000000&p=2 (717 words)

	[No title]
		When branch removal is not possible, the branch can be coded to help the processor predict it correctly based on the static branch prediction rules.
		As a rule of thumb, remove or optimize a branch if the branch mispredict ratio is greater than about 8% and the location of the branch is a hotspot in the execution profile relative to the rest of the code.
		It is important to consider both the metrics together because a branch location may be an execution hotspot simply due to the fact that it is execute frequently, even though it is never mispredicted.
	www.intel.com /cd/ids/developer/asmo-na/eng/downloads/code/languages/19952.htm?page=2 (457 words)

	ONLamp.com -- Getting Familiar with GCC Parameters
		The goal of this procedure is to eliminate as many mispredicted branches as possible, thus improving pipeline utilization.
		However, for most modern processors, this kind of transformation is not terribly necessary because the branch predictor is smart enough on its own.
		Oprofile is executed to record the number of retired branches and retired mispredicted branches.
	www.onlamp.com /pub/a/onlamp/2007/04/03/getting-familiar-with-gcc-parameters.html (1342 words)

	IBM JRD 49-4/5 \| Characterization of simultaneous multithreading (SMT) efficiency in POWER5
		When the branch instruction is actually evaluated, it may be the case that the wrong path was taken for speculation; this is referred to as a branch misprediction.
		After a branch misprediction is discovered, all instructions following the branch are flushed from the execution pipeline and execution begins again along the correct path.
		As a result, fewer instructions are discarded when the branch instruction is evaluated and a branch misprediction is found, and this makes the pipelines appear less busy in SMT mode.
	www.research.ibm.com /journal/rd/494/mathis.html (5924 words)

	[No title]
		In these conditional branches, there are two possible ‘next’ instructions and in general we don't know which one is the correct path.
		Typically the cost of a branch mispredict is close or equal to the total length of the pipeline.
		As branch prediction accuracy degrades, the tradeoff for the loss of hardware by running the wrong branch becomes less significant than the losses due to branch mispredicts.
	www.eden.rutgers.edu /~winter37/Arc-report-2003.doc (3078 words)

	More to Prescott Than Meets the Eye: Pipelines and Predictions (Site not responding. Last check: 2007-11-05)
		Static branch prediction (a technique that relies on prior knowledge of branch behavior before actual program execution, such as knowing most loops branch backwards) was improved in Prescott.
		In prior P4 static branch prediction algorithms, backwards branches were assumed to be part of loops, but that's not always the case.
		If the branch was not included in the BTB and must be statically predicted, a check is made on both branch direction and branch distance.
	www.extremetech.com /article2/0,1697,1530636,00.asp (1034 words)

	Spartanburg SC \| GoUpstate.com \| Spartanburg Herald-Journal (Site not responding. Last check: 2007-11-05)
		Branch misprediction occurs when a Central processing unit (CPU) mispredicts the next instruction to process in branch prediction, which is aimed at speeding up execution.
		When the code for a conditional jump is read we do not yet know the next instruction to execute and insert into the execution pipeline.
		Branch prediction guesses the next instruction to execute and inserts the next assumed instruction to the pipeline.
	www.goupstate.com /apps/pbcs.dll/section?category=NEWS&template=wiki&text=branch_misprediction (146 words)

	Main Page - Linux Troubleshooting
		But branch prediction is not always correct, and some branches are hard to predict.
		This causes num_proc2 to not always be equal to 1, and hence branch misprediction occurs in the parent thread.
		Similarly, toggling the value of num_proc1 by the parent thread causes branch misprediction in the clone thread.
	www.linuxtroubleshooting.com /wiki/index.php?title=Main_Page (11172 words)

	Comp.compilers: Re: Avoiding Branch Misprediction in Virtual Machine (VM) Portably
		Re: Avoiding Branch Misprediction in Virtual Machine (VM) Portably anton@mips.complang.tuwien.ac.at (2007-05-13)
		Re: Avoiding Branch Misprediction in Virtual Machine (VM) Portably eliotm@pacbell.net (Eliot Miranda) (2007-05-14)
		the branch prediction by the BTB and causes the performance regression
	compilers.iecc.com /comparch/article/07-05-046 (486 words)

	Branch misprediction (Signifying Nothing: Tell 'em about it, Joe-Joe!) (Site not responding. Last check: 2007-11-05)
		Branch misprediction (Signifying Nothing: Tell 'em about it, Joe-Joe!)
		Nothing definite, but playing the odds in the presence of asymmetrical payoffs for misprediction seems like a bad idea at this point—potentially wasting hours of my life on applications beats potentially having to beg for a job at Best Buy or Red Hat, any day.
		On the upside, a whole new vista of postdocs and one-years have been opened to me. Happy happy, joy joy.
	blog.lordsutch.com /archives/3204 (316 words)

	Comp.compilers: Avoiding Branch Misprediction in Virtual Machine (VM) Portably
		Comp.compilers: Avoiding Branch Misprediction in Virtual Machine (VM) Portably
		Avoiding Branch Misprediction in Virtual Machine (VM) Portably
		Or make the code a list of function pointers, so it's
	compilers.iecc.com /comparch/article/07-05-044 (270 words)

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