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	Branch predictor - TheBestLinks.com - Branch prediction, Computer architecture, MIPS architecture, Processor, ...
		In computer architecture, a branch predictor is the part of a processor that determines whether a branch in the instruction flow of a program is likely to be taken or not.
		Branches evaluated as not taken decrement the state towards strongly not taken, and branches evaluated as taken increment the state towards strongly taken.
		Combined predictors with different indexing functions for the different predictors are called gskew predictors, and are analogous to skewed caches used for data and instruction caching.
	www.thebestlinks.com /Branch_prediction.html (2047 words)

	Branch predictor - Wikipedia, the free encyclopedia
		In computer architecture, a branch predictor is the part of a processor that determines whether a conditional branch in the instruction flow of a program is likely to be taken or not.
		Branch predictors are crucial in today's modern, superscalar processors for achieving high performance.
		Branch prediction is not the same as branch target prediction.
	en.wikipedia.org /wiki/Branch_prediction (2205 words)

	Branch predictor (Site not responding. Last check: 2007-10-19)
		Branch predictors are crucial intoday's modern, superscalar processors for achieving high performance.
		Branches evaluated as not taken decrement the state towardsstrongly not taken, and branches evaluated as taken increment the state towards strongly taken.
		Because the next line predictor is so inaccurate, and the branch resolution recurrence takes so long,both cores have two-cycle secondary branch predictors which can override the prediction of the next line predictor at the cost ofa single lost fetch cycle.
	www.therfcc.org /branch-predictor-346175.html (1904 words)

	Branch predictor using random access memory - Patent 4370711
		Thus, when it is known that a branch is taken, the count that is addressed in the RAM is incremented unless it reaches a predetermined value of +q, in which case the count is left at +q.
		If the branch is not taken, the count which is addressed in the RAM is decremented unless it is already a predetermined quantity -p, in which case the count is left at -p.
		The branch predictor receives as an input a signal on control line 18 to indicate whether or not the previous branch instruction was taken or not.
	www.freepatentsonline.com /4370711.html (2928 words)

	Irisa : thèse proposée pour la rentrée 2001
		Unfortunately it is unlikely that such predictor would be able to deliver a result in less than 3 or 4 cycles.
		Usual branch predictors uses information (branch histories, fetch addresses,..) available at a cycle to generate the next fetch addresses.
		It should also be noted that when complexifying the branch predictor results in an increase of its crossing latency, the extra accuracy may be counterbalanced by extra bubbles in pipeline front-end.
	www.irisa.fr /theses2001/caps2.htm (496 words)

	A Branch Prediction Simulation Study: MIPS R10000 vs. Alpha 21264 (Site not responding. Last check: 2007-10-19)
		The basic layout of the MIPS R10000 branch predictor [3] is a 256 entry, 4-way set associative branch target buffer (BTB) and a 2048 entry, 2-bit, pattern history (PH) table.
		The global predictor in the 21264 [2] contains 4K entries indexed by the history of the last 12 branches, where each entry is a 2-bit up-down saturating counter.
		So, the result is that all the predictors that are not the most common, and in a 256 entry cache that is not many instructions, will always map to the same, small number of spots in the pattern history table.
	www.cs.uoregon.edu /~catchen/cis629 (2121 words)

	Branch predictor -- Facts, Info, and Encyclopedia article (Site not responding. Last check: 2007-10-19)
		Branch prediction is not the same as (Click link for more info and facts about branch target prediction) branch target prediction.
		branch predictors, and merge their results by a majority vote.
		branch because the branch resolution recurrence was four cycles long.
	www.absoluteastronomy.com /encyclopedia/B/Br/Branch_predictor.htm (1988 words)

	Branch Target Predictor Encyclopedia Article, Definition, History, Biography (Site not responding. Last check: 2007-10-19)
		In computer architecture, a branch target predictor is the part of a processor that predicts the target of a conditional branch or unconditional jump instruction before that instruction has been fetched from the instruction cache.
		Branch prediction attempts to guess whether the branch will be taken or not.
		As the predictor RAM can be 5-10% of the size of the instruction cache, the fetch happens much faster than the instruction cache fetch, and so this recurrence is much faster.
	www.karr.net /encyclopedia/Branch_target_predictor (505 words)

	Into the Core: Intel's next-generation microarchitecture : Page 7
		This is because when a branch is mispredicted, it takes a relative eternity to retrieve the correct branch target from main memory; during this lengthy waiting period, a single-threaded processor must sit idle, wasting execution resources and power.
		The branch history tables used in normal branch predictors don't store enough branch history to be able to correctly predict loop termination for loops beyond a certain number of iterations, so when the loop terminates they mispredict that it will keep going based on its past behavior.
		Because indirect branches load their branch targets from a register, instead of having them immediately available as is the case with direct branches, they're notoriously difficult to predict.
	www.cs.umbc.edu /~squire/images/core.ars7.htm (603 words)

	CBP_CFP
		Contestants will be given a fixed storage budget to implement their best branch prediction algorithms on a common evaluation framework distributed by the CBP steering committee.
		The goal of the Championship Branch Prediction competition is to evaluate and compare branch prediction algorithms in a common framework.
		Predictors must be implemented within a fixed storage budget, and will be judged on performance.
	www.jilp.org /cbp (522 words)

	SIMPLE SCALAR
		Simulations are run on the three benchmarks specifying the branch predictor to be one of always taken, always untaken, bimodal predictor using a branch target buffer, or a 2-level adaptive predictor.
		The effect of the size of the BTB on the number of mispredicted branch directions is observed by running all the benchmarks varying the size of the BTB to be 256, 512, 1024, 2048, 4096 and 8192 bytes.
		In addition to the effectiveness in prediction, a bimodal predictor reduces the branch penalty and hence the total execution time since the next instruction address is known in the ID stage itself.
	www.ece.uci.edu /~pgontla/ss.html (1568 words)

	Evaluation of branch-prediction methods on traces from commercial applications
		Interrupts as such are not problematic for branch prediction, but due to the completely different address range, they may force replacement of a branch from a finite history table that may be needed again after the interrupt service routine is completed and the original task has resumed.
		In [5], Nair proposed a scheme in which the taken/not taken type of branch history from the previous chapter is replaced by a history representing the path leading to the branch to be predicted.
		As with adaptive prediction of branch directions, where a history pattern is used to define the entry in a pattern table which then predicts the branch outcome, Chang suggested the use of a history pattern to select the correct target address from among several target addresses stored for that branch.
	www.research.ibm.com /journal/rd/434/hilgendorf.html (7186 words)

	Paper: Co & Skadron, "The Effects of Context Switching on Branch Predictor Performance" (Site not responding. Last check: 2007-10-19)
		Accurate simulation of branch prediction is important because branch prediction strongly influences the behavior of processor structures.
		A thorough characterization of the effects of branch predictor configuration, branch predictor area, and time slice length is provided.
		As further verification, branch predictor performance with and without flushing the predictor structures is compared.
	www.cs.virginia.edu /~skadron/Papers/contsw_bpred2001.abstract.html (216 words)

	Branch prediction in the Pentium family (Site not responding. Last check: 2007-10-19)
		The branch instruction is predicted to jump next time if in state 2 or 3, and to not jump when in state 0 or 1.
		The branch instruction is predicted to jump next time if the counter is in state 2 or 3, and to not jump if in state 0 or 1.
		The most important shortcoming of the two-level branch prediction is that it is not very good at predicting the branch pattern of a loop control.
	www.x86.org /articles/branch/branchprediction.htm (1921 words)

	Energy Citations Database (ECD) - Energy and Energy-Related Bibliographic Citations
		Branch classification allows an individual branch instruction to be associated with the branch predictor best suited to predict its direction.
		Using this approach, a hybrid branch predictor can be constructed such that each component branch predictor predicts those branches for which it is best suited.
		To demonstrate the usefulness of branch classification, an example classification scheme is given and a new hybrid predictor is built based on this scheme which achieves a higher prediction accuracy than any branch predictor previously reported in the literature.
	www.osti.gov /energycitations/product.biblio.jsp?osti_id=273919 (300 words)

	A Look at Centrino's Core: The Pentium M: Page 3
		One problem with static branch predictors is that they always make a wrong prediction on the final iteration of the loop--the iteration on which the branch evaluates to "not taken"--thereby forcing a pipeline stall as the processor recovers from the erroneous prediction.
		Dynamic predictors, like the P4's branch predictor, fix this by shortcoming by keeping track of the execution history of a particular branch instruction--whether it was "taken" or "not taken" the past few times it was evaluated--in order to give the processor a better idea of what its outcome on the current pass will probably be.
		One of the main shortcomings of the P4's branch predictor is that, even though its BHT is relatively sizeable, it doesn't have enough space to store all the relevant execution history information on the loop branches that tend to take a very large number of iterations.
	arstechnica.com /articles/paedia/cpu/pentium-m.ars/3 (1038 words)

	Microbenchmarks for determining branch predictor organization, LaCASA Lab
		Although dynamic branch predictors are designed with the aim to automatically adapt to changes in branch behavior during program execution, code optimizations based on the information about predictor structure can greatly increase overall program performance.
		This paper presents an experiment flow with a series of microbenchmarks that determine the organization and size of a branch predictor using on-chip performance monitoring registers.
		The described approach can also be used during processor design for performance evaluation of various branch predictor organizations and for testing and validation during implementation.
	www.ece.uah.edu /~lacasa/bp_mbs/bp_microbench.htm (236 words)

	[No title]
		The usefulness of the branch predictor is dependant on the type of code being run but paradoxically the OOO hardware can act against it.
		Branch predictors are not useless (they wouldn’t be used otherwise) so the PPE does include one.
		While the lack of OOO and a large branch predictor will have some impact, the ability to run a second thread will make up for it at least partially as a second thread can utilise the full execution resources while the first thread is waiting.
	www.blachford.info /computer/Cell/Cell4_v2.html (2870 words)

	The Effects of Context Switching on Branch Predictor Performance
		Branch prediction is one of the most powerful and widely-used techniques, which "guesses" the outcome of a branch before its condition is resolved.
		Therefore, accurate branch prediction is critical to higher performance, and it has been suggested that branch prediction accuracy is the biggest single architectural lever over performance in uniprocessors.
		This project systematically characterizes the effects context switching has on the performance of various branch predictor configurations and explains these effects by showing that the training time required by branch predictors is under 128K instructions, much shorter than current time slices.
	www.intercom.virginia.edu /colloquia/event156.html (218 words)

	Branch Prediction Research in the LAVA Lab (including hybrid predictors, speculative update, return address stack, and ...
		Improving branch prediction, although already a well-studied subject, remains critical because delivering very high branch-prediction rates is crucial to further performance gains in high-performance computing.
		branch predictor structure—a pseudo-hybrid branch predictor that we call an alloyed predictor.
		Not only do some branches in a program benefit from global history while others benefit from local history—a well known fact that suggests use of a hybrid predictor—but in fact individual branches vary between benefiting from global history and benefiting from local history.
	lava.cs.virginia.edu /bpred.html (819 words)

	[No title] (Site not responding. Last check: 2007-10-19)
		For the 1-bit and 2-bit schemes, entries in the BTB tables are only initially created when a branch is first taken (non-taking branches will by default be predicted as non-taken since they have no previously created table entry).
		In the case of the GAg predictor, the 8-bit history register is shared by all of the branches executing.
		Therefore for a correctly predicted branch (a fall thru with no BTB entry is a correct prediction), and a 1 + 5 = 6 cycle penalty for misprediction.
	ece-www.colorado.edu /~ecen5593/project/project1.html (519 words)

	CPU Cache Encyclopedia Article, Definition, History, Biography (Site not responding. Last check: 2007-10-19)
		As is usual for this class of CPU, the K8 has fairly complex branch prediction, with tables that help predict whether branches are taken and other tables which predict the targets of branches and jumps.
		The net result is that the branch predictor has a larger effective history table, and so has better accuracy.
		Some of the terminology used when discussing predictors is the same as that for caches (one speaks of a hit in a branch predictor), but predictors are not generally thought of as part of the cache hierarchy.
	encyclopedia.localcolorart.com /encyclopedia/CPU_cache (6811 words)

	Assignment 1: Pipelines and Branch Prediction
		The first part requires you to code up 3 different branch predictors, one that works on information gathered for each branch in the program (a so called "local" predictor), and one that works by correlating between different branches (a "global" predictor), and one that is a hybrid of the two (a "tournament" predictor).
		To update the predictor (so that it can learn), you update the same 2-bit counter used to perform the prediction using the direction of the branch.
		As part of this predictor you must have both of the predictors described above (you are free to change the parameters, but the method of prediction should be unchanged).
	www.cs.ucsb.edu /~arch/cs254/a1 (2172 words)

	Multi-hybrid branch predictor (Site not responding. Last check: 2007-10-19)
		A hybrid predictor with several components can solve this problem by using component predictors with shorter warm-up times while the larger predictors are warming up.
		Examples of predictors with shorter warm-up times are two-level predictors with shorter histories as well as smaller dynamic predictors.
		The Multi-Hybrid uses a set of selection counters for each entry in the branch target buffer, in the trace cache, or in a similar structure, keeping track of the predictor currently most accurate for each branch and then using the prediction from that predictor for that branch.
	www.csd.ijs.si /courses/processor/Chapter5/sld023.htm (142 words)

	Better Branch Prediction Through Prophet/Critic Hybrids
		The prophet/critic hybrid conditional branch predictor has two component predictors.
		The critic uses the branch's history and future to critique the prophet's prediction.
		The hybrid combines the prophet's prediction with the critique, either agree or disagree, forming the branch's overall prediction.
	csdl2.computer.org /persagen/DLAbsToc.jsp?resourcePath=/dl/mags/mi/&toc=comp/mags/mi/2005/01/m1toc.xml&DOI=10.1109/MM.2005.5 (485 words)

	Paper: Co, Weikle, & Skadron, "A Break-Even Formulation for Evaluating Branch Predictor Energy Efficiency" (Site not responding. Last check: 2007-10-19)
		Consequently, understanding the tradeoff between reduced mis-speculation, execution time, and increased power spent within a branch predictor is critical.
		By calculating a \emph{break-even} branch predictor energy budget for a given program and an energy-efficiency target, we are able to evaluate the energy-efficiency of several existing branch predictor designs and provide a simple way to think about energy-efficiency.
		Furthermore, we develop a method for deriving a branch predictor energy budget without requiring a power model for the proposed branch predictor.
	www.cs.virginia.edu /~mc2zk/pubs/breakeven_bpred2005.abstract.html (221 words)

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