| | Formal validation of virtual finite state machines |
 | | Index Terms- formal specification; software tools; telecommunication computing; finite state machines; program verification; electronic switching systems; formal validation; virtual finite state machines; formal validation tool; ATandT; 5ESS; telephone switching system; communicating processes; virtual finite state machine; super-trace algorithm; process interaction; deadlock; livelock; unexpected inputs; message buffer overflow; unreachable code; software development |
 | | The tool validates networks of communicating processes implemented in the virtual finite state machine (VFSM) notation, using Holzmann's (1991) super-trace algorithm to check for errors in process interaction such as deadlock, livelock, unexpected inputs, message buffer overflow, and unreachable code. |
 | | We discuss the extent to which the validator has been successfully employed in 5ESS software development, and describe our present research efforts to eliminate some of the roadblocks that stand in the way of its more widespread use. |
| doi.ieeecs.org /DOIResolver/resolver/10.1109/WIFT.1995.515484 (236 words) |