| | Semiconductor memory device for providing burst mode control signal, device comprising plural serial transition ... |
 | | That is, the burst mode control signal ADV is reset to its initial state by the combination of the output signal generated from an invertor 105, which inverts the chip enable signal CE, which is input to an AND gate 106 along with the ADSC signal. |
 | | In the embodiment of the present invention illustrated herein, the burst mode control signal ADV is generated for a duration of three clock cycles of the clock signal CK in order to control a counter which generates successive addresses for three cycles after the read/write operation is initiated. |
 | | That is, a burst mode control signal ADV having a predetermined pulse length can be generated by varying the number of transition registers within the burst mode control signal generating circuit of the present invention. |
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