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Topic: Bus contention

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Computer bus

Front side bus

Southbridge (computing)

Northbridge (computing)

PCMCIA

PC motherboard

	Ken's Dictionary of Computer Standards
		CPU's are classified by their instruction set width, integer data register size, data bus width, address bus width, and the clock speed at which they access data.
		Unfortunately the 8.25MHz bus speed made for high latency in small transfers, leading to poor video performance compared to the 32 bit, 33 MHz VESA Local bus.
		A set of 16 lines on the PC Bus, that when asserted by the I/O device, notifies the CPU that the device is in need of servicing.
	www.charm.net /~kmarsh/dict.html (5119 words)

	Bus contention - Wikipedia, the free encyclopedia
		Bus contention is an undesirable state of the bus of a computer, in which more than one memory mapped device or the CPU is attempting to place output values onto the bus at once.
		Normally, integrated circuits that connect to the bus are designed so that the likelihood of bus contention is nil provided that the chips are operated within their rated set-up times and so forth.
		Contention may also arise on a system whose memory mapping is programmable, and illegal values are written to the registers controlling the mapping.
	en.wikipedia.org /wiki/Bus_contention (153 words)

	Computer bus - Wikipedia, the free encyclopedia
		The former referred to bus systems that were designed to be used with internal devices, such as graphics cards, and the latter to buses designed to add external devices such as scanners.
		An internal bus connects all the internal components of a computer to the motherboard (and thus, the CPU and internal memory).
		These types of buses are also referred to as a local bus, because they are intended to connect to local devices, not to those in other machines or external to the computer.
	en.wikipedia.org /wiki/Computer_bus (1947 words)

	esp@cenet description view
		That is, the bus grant signal BG inputs of both the ports supplied via gates G16 and G17 are subjected to an AND operation by gate G18 and the output is delivered to the processor as the bus grant signal BG input of the processor.
		The bus contention signal BCNTN output of the processor 11 and the bus contention signal BCNTN input of each port are subjected to an OR operation by gates G24 and G25 and delivered via respective gates G26 and G27 to the port opposite to the input port.
		In this manner, the "off" condition of the bus grant signal BG is relayed from the port 7 to the port 6 and then to the port 4 and is supplied to the relay bus controller unit 5 of the processor 11.
	v3.espacenet.com /textdes?&DB=EPODOC&IDX=EP103803 (5703 words)

	Bus
		Bus contention Bus contention is an undesirable state of the registers controlling the mapping.
		Bus network A bus network is a network architecture in which a set of clients are connected via a shared communications...
		Jerusalem bus 20 massacre The Jerusalem bus 20 massacre was a 2002.
	www.brainyencyclopedia.com /topics/bus.html (1267 words)

	Patent 4550402: Data communication system
		Once it is determined that the contention bus is clear, the contention bus interface module transmits a mini-packet on the contention bus and monitors a dedicated CONTROL line for an acknowledgment signal, for a period of time before the end of the access period.
		A receiving amplifier 102 is provided in the bus interface circuit 100 to receive data from the corresponding host computer and its local network for transmission to one or more of the other addressable local networks connected to the contention bus 10 through their respective bus interface circuit 100.
		Efficient use of the contention bus is made by the transmission of low overhead mini-packets as a single unit and then releasing access of the bus for another local network to use while the next mini-packet is being formatted for transmission.
	www.freepatentsonline.com /4550402.html (6145 words)

	World Intellectual Property Organization (Site not responding. Last check: 2007-10-10)
		Of course, regarding references to a bus"having","employing", etc. a contention scheme it should be understood that such contention schemes are typcially provided and enforced by bus controller circuits coupled to the bus, and devices coupled to the bus which cooperate with the bus controller.
		A method includes setting a contention scheme for an asynchronous bus such that the contention delay of isochronous transactions on the bus is bounded, and establishing an isochronous interface between at least two devices, the isochronous interface supporting an X-T contract.
		The system of claim 11 in which the contention scheme for the bus further comprises: a maximum number of read request transactions and write request transactions which may be received sequentially by the bus.
	www.wipo.int /ipdl/IPDL-CIMAGES/view/pct/getbykey5?KEY=01/27776.010419&ELEMENT_SET=DECL (5639 words)

	Patent 4096571: System for resolving memory access conflicts among processors and minimizing processor waiting times ...
		Each contention circuit has a comparator for comparing its waiting time value with the time value on the bus and means to disable the respective contention logic circuit when the comparison shows that the wait bus value is greater.
		In this example the "bus request" signal was present from the processor for three "wait clock" periods before the bus grant occurred and the "bus request" signal was removed.
		The hard wiring for bus contention is constructed to accommodate the maximum number, 4, and thus with the position 20.sub.ii blank, inhibit output 21.sub.i from module 20.sub.i terminates at an open connector 23.
	www.freepatentsonline.com /4096571.html (6954 words)

	Patent 4463445: Circuitry for allocating access to a demand-shared bus
		It is known to use distributed bus allocation arrangements in which a controller is not used to determine access and instead, the interaction of the requesting ports determines bus allocation in the event of simultaneous requests.
		During bus contention times, the bits in the shift register of each requesting port are read out sequentially one at a time beginning with the most significant bit and applied to the arbitration bus.
		The bus is effective when activated to cause the associated port to be removed from service and to deny it access to the arbitration bus 102 and the packet busses 105 and 106.
	www.freepatentsonline.com /4463445.html (8484 words)

	Simulation-Based Evaluation
		The actual contention for the kernel data structures in our current implementation is low and we did not have the ability to create high contention at the time of writing.
		In this case the difference between the non-concurrent algorithms is simply the bus contention and the fixed overhead because we are not modelling page faults.
		The bus and memory contention are so much greater that the concurrency does not gain enough to offset the loss due to overhead.
	www-dsg.stanford.edu /papers/non-blocking-osdi/node16.html (1062 words)

	Patent 4667191: Serial link communications protocol
		Specifically, the problems to be addressed were those of transmission economy, bus contention, error detection and subsystem device addressing.
		A final object of the invention is to simplify bus contention.
		This implies that when the bus is sensed to be idle, any device wishing to initiate a transmission may asynchronously do so at any moment.
	www.freepatentsonline.com /4667191.html (1933 words)

	Boston.com / News / Politics / Conventions / Searches underway on buses to Hub (Site not responding. Last check: 2007-10-10)
		The Vermont Transit bus company also plans random baggage inspections from its terminal in White River Junction, Vt., for Boston-bound buses, and officials at Springfield-based Peter Pan bus lines expect to discuss inspections in a meeting with the Transportation Security Administration scheduled for today.
		The inspections of the five Boston-bound commuter buses in Londonderry yesterday morning clearly indicated that bus travel, at least during the period around the convention, will be subject to a new level of scrutiny.
		For the T's 1,035 buses and 174 bus routes in Greater Boston, passengers should expect to be randomly stopped to have bags inspected before boarding, Pesaturo said.
	www.boston.com /news/politics/conventions/articles/2004/07/08/searches_underway_on_buses_to_hub (785 words)

	www.openbmw.org / I-Bus
		The I-Bus is a single wire bus that is a white/red/yellow wire which is available at a number of different connectors inside the car such as at the CD changer connector in the rear, the phone connector in the center console, etc.
		The bus' physical layer is an open collector setup pulled high (+12v) by the bus, and pulled low by the talker.
		Because the I-Bus uses the physical layer of the ISO9141/K-Bus, it is fairly easy to build a connector from off-the-shelf IC parts or to even potentially take an existing OBD-2/RS232 adapter and connect the K-Line from it to the I-Bus.
	www.openbmw.org /bus (804 words)

	CHAPTER THREE: SYSTEM ORGANIZATION (Part 5)
		Executing instructions in parallel using a bus interface unit and an execution unit is a special case of pipelining.
		Bus contention occurs whenever an instruction needs to access some item in memory.
		The CPU uses the data/address bus only when reading a value which is not in the cache or when flushing data back to main memory.
	www.arl.wustl.edu /~lockwood/class/cs306/books/artofasm/Chapter_3/CH03-5.html (2896 words)

	Contention
		Chu-Han contention This article should be merged with Chu-Han War The Chu-Han contention (楚漢相୪...
		Contention In telecommunication, the term contention has the following meanings: 1.
		Contention free pollable Contention-free pollable (CF-Pollable) is IEEE 802.11b standard uses CSMA /CA or carrier sens...
	www.brainyencyclopedia.com /topics/contention.html (65 words)

	[No title]
		The impact of architectural bottlenecks was more profound on the SGI multiprocessor (as shown in Section 6) than on the Alliants, mostly due to the cost of enforcing cache coherence (a problem that does not exist for the Alliants which use shared cache), and the limited bus bandwidth.
		Bus contention was measured by comparing the performance of two almost identical loop kernels which are shown in Figure 8.
		Although we attempted to separate the performance loss due to cache misses from that due to bus contention, it was not possible to measure events at the level of clock period with software timers.
	www.chg.ru /SC95PROC/025_KUBA/SEC4.HTM (1304 words)

	The Right Bus In The Right Place: a Tutorial (part 1) (Site not responding. Last check: 2007-10-10)
		The bus qualifies as a processor bus, a memory extension bus or a (non intelligent) I/O bus.
		We define bus load as the percentage of time the bus is in use for actual transfers, cycles or transactions.
		Suppose bus arbitration is done without losing time (which should be the case in parallel busses, but is rarely the case in practice [3]) then 100% bus-time is available for these two processors.
	www.realtime-info.be /magazine/96q4/right_bus1.htm (2476 words)

	Novas Software: Newsletter (Site not responding. Last check: 2007-10-10)
		Bus contention problems result when a signal or bus has multiple active drivers at the same time.
		Identifying the errors due to bus contention takes a lot of time and effort.
		The bus and the active drivers are then isolated and displayed on a flat schematic for easy viewing and analysis.
	www.novas.com /.docs/pg/10154 (138 words)

	IDT and Micron Introduce New Smart ZBT SRAM Technology (Site not responding. Last check: 2007-10-10)
		Bus contention occurs if the ASIC does not get off the bus prior to the SRAM getting on the bus.
		Smart ZBT SRAMs reduce the potential for bus contention by allowing the output turn-on of the SRAM to adapt to the user's system.
		In addition, all critical timing parameters for ZBT SRAMs are referenced to the rising edge of the synchronous clock, which simplifies the design of high-bandwidth switching systems.
	www.micron.com /News/product/1999-08-23_16248.html?print=yes (770 words)

	ICUII Video Chat : The live video window in any video application is green, or live video freezes frequently, and can ...
		Manufacturers can improve the performance of their graphics cards by holding the PCI bus as long as possible within the PCI Specification guidelines.
		If there is not room for the command then the bus master will not release the bus until it can transmit the command to the video card.
		There are a number of steps you can take that may help to resolve the PCI Bus Contention issue.
	www.icuii.com /help/faq/answer.php?faqid=45 (292 words)

	Performance Model for a Prioritized Multiple-Bus Multiprocessor System (ResearchIndex)
		The effect of bus and memory contention is modeled using a probabilistic model and a closed form solution for the acceptance probability of each processor is presented.
		Whenever a request from a processor is rejected due to bus or memory...
		7 Modeling bus contention and memory interference in a multipr..
	citeseer.ist.psu.edu /98392.html (549 words)

	Method for avoiding bus contention in a digital circuit (US6104210)
		In a digital circuit, a method for avoiding a bus contention condition which results from an overlap of active phases of multiple bus drivers.
		The method avoids such bus contention condition by including holding amplifiers in the data bus and by turning on respective bus drivers only for durations sufficient to establish a data value on the data bus.
		including for each bit of said data bus a holding amplifier, said holding amplifier maintaining a data value of said bit, when neither said first bus driver nor said second bus driver is active; and
	www.delphion.com /details?pn=US06104210__ (256 words)

	[No title] (Site not responding. Last check: 2007-10-10)
		I simulate a ring topology on a common bus in solving the N-body problem in astrophysics.
		Here is a time table and a model of communication on the system WITHOUT BUS CONTENTION.
		For example, in this histogram problem, we reduce bus contention by using a tree structure which yields O(lgn) instead of O(n).
	www.cs.tufts.edu /~sanpawat/spring1999.html (1028 words)

	Ultra Fast Linux Friendly Web Site Hosting
		On those PCI bus machines, DMA devices first have to load data into kernel address space, and then the CPU has to copy that block to user address space.
		One is intended for general viewing and the other is intended specifically for adult content.
		Nudity, sexual content, graphic violence, or anything else not suitable to audiences of all ages should not be placed in this directory.
	www.eskimo.com /services/hosting.html (1688 words)

	Bus Contention
		A bus conflict occurs when the pin from the PIC driving Data In and the Data Out from the EEPROM are both active at the same time.
		It's even worse when one is set to high and the other to low because it causes a short which of course is very very bad for the circuit.
		BTW this bus conflict is always a transient event because Data Out is usually tri-stated when not in use.
	techref.massmind.org /io/contention.htm (426 words)

	Intel Create & Share® Camera Pack 1.0 USB - PCI Bus Contention
		If there is not room for the command then the bus master will not release the bus until it can transmit the command to the video card.
		However, in the case of the Intel® USB camera that is included with the Intel® Create and Share® Camera Pack, you may experience "PCI bus contention" problems.
		However, in the case of Intel's USB cameras, you may experience "PCI bus contention" problems.
	support.intel.com /support/createshare/camerapack/usb/sb/cs-011534.htm (869 words)

	ePanorama.net :: View topic - PIC PSP port bus contention
		It would seem that you are driving the bus with both devices at the
		has control of the bus at any given time.
		It seemed to me that the external flag system to the bus was poorly
	www.epanorama.net /phpBB2/viewtopic.php?p=14971 (830 words)

	[SunRescue] Ross SM100 CPU Module Question (Site not responding. Last check: 2007-10-10)
		You can work around VME contention more easily than P2 contention, technically you should not even need to pull BG/IACK on an intermediate slot.
		I _think_ that there is an easy way to disable the P2 bus on a 600, but I'd have to dig through my schematics to find out.
		This would let you cram 8 boards in a chassis (16 slot) instead of 4 (the max number of seperate P2 busses).
	www.sunhelp.org /pipermail/rescue/1999-June/001189.html (207 words)

	AB-66 Resolving Bus Contention When Interfacing the Intel386™ EX Embedded Processor with Intel Flash
		Examining the worst-case timing relations for interfacing the Intel386™ EX embedded processor with flash indicates bus contention on a memory read followed by a memory write.
		However, the Intel386 EX embedded processor specification t50 resolves this issue and guarantees no bus contention if the flash data float time (tGHQZ) is less than or equal to t50.
		This document explains why there is no contention when interfacing with Intel Flash.
	www.intel.com /design/intarch/applnots/292197.htm (110 words)

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