| | Paul Hsieh's 6th generation x86 CPU Comparisons |
 | | In keeping with their post-RISC architecture, the P-II's have in some cases increased the latency of some of the FPU instructions over the Pentium for sake of pipelining at high clock rates and with idea that it hopefully will not matter if the code is properly scheduled. |
 | | The P-II architecture is getting long in the tooth, but Intel keeps insisting on pushing it (demonstrating an uncooled 650Mhz sample in early 1999.) Mum's the word on Intel's seventh generation x86 architecture (the Williamette or Foster) probably because that architecture is not scheduled to be ready before late 2000. |
 | | This is because on older architectures, they hurt you no matter what, with no opportunity for instruction overlap, so the rule of avoiding them as much as possible was more important than knowing the precise penalty. |
| www.azillionmonkeys.com /qed/cpuwar.html (11012 words) |