CPU modes - Factbites

CPU modes - Factbites
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Topic: CPU modes

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	DTJF03SC.TXT
		Lock modes are implemented through a dynamic lock configuration scheme that essentially installs the appropriate set of lock primitives for the selected lock mode.
		Locking or unlocking a spin lock multiple times or not unlocking it at all (usually in code loops) would disable preemption well beyond the end of a critical section or enable it before the end.
		A lock class's position in the lockinfo table is also its position in the lock hierarchy; that is, locks must be taken in the order in which they appear in the table.
	www.research.compaq.com /wrl/DECarchives/DTJ/DTJF03/DTJF03SC.TXT (8408 words)

	CPU Speed
		A faster CPU will run these benchmarks faster than a slower one, and I have found it to be quite consistent that testing the same drive on a machine with a much faster CPU, will result in higher scores.
		The reason is that the CPU is so much faster than anything related to the hard disk, particularly today, that it normally spends a great deal of time waiting for the hard disk.
		And even today, if an interface mode is used that results in high CPU utilization by the hard disk interface, overall performance can become somewhat dependent on the performance level of the CPU itself.
	www.storagereview.com /guide2000/ref/hdd/perf/perf/ext/pcCPU.html (8408 words)

	Great Microprocessors of the Past and Present
		The AMD 29000 is another load-store CPU descended from the Berkeley RISC design (and the IBM 801 project), as a modern successor to the earlier 2900 bitslice series (beginning around 1981).
		Later, Motorola designed a successor called Coldfire (early 1995), in which complex instructions and addressing modes (added to the 68020) were removed and the instruction set was recoded, simplifying it at the expense of compatibility (source only, not binary) with the 680x0 line.
		It was designed as a single chip version of the TI 990 minicomputer series, much like the Intersil 6100 was a single chip PDP-8, and the Fairchild 9440 and Data General mN601 were both one chip versions of Data General's Nova.
	bwrc.eecs.berkeley.edu /CIC/archive/cpu_history.html (15782 words)

	W.Ehrhardt: Crypto
		All chaining modes allow plain and cipher text lengths that need not be multiples of the block length (for ECB and CBC cipher text stealing is used for the short block; only one short block is allowed and there must be at least one full block).
		All modes allow plain and cipher text lengths that need not be multiples of the block length (for ECB and CBC cipher text stealing is used for the short block).
		With t_gspeed the CPU cycles per block and the (theoretical) encryption speed in MB/s were measured for the different compilers (this program needs the high resolution timer routines from hrtimer).
	home.netsurf.de /wolfgang.ehrhardt/crypt_en.html (1205 words)

	Using X
		For planar modes, vgaemu has to switch to part ial cpu emulation.
		Modes that are defined but cannot be supported due to lack of video memory or because they cannot be displayed on your X display, are marked as unsupported in the VBE mode list (but are still in it).
		Hi-color modes are supported only on displays matching the exact color depth (15 or 16); true color modes are supported only on true color X displays, but always both 24 bit and 32 bit SVGA modes.
	dosemu.sourceforge.net /docs/README/1.2/x478.html (1716 words)

	Programmed input/output - Wikipedia, the free encyclopedia
		The PIO modes require a great deal of CPU overhead to configure a data transaction and transfer the data.
		The programmed input/output (PIO) interface was the original method used to transfer data between the CPU (through the IDE controller) and an IDE/ ATA device.
		The PIO interface is grouped into different modes that correspond to different transfer rates.
	en.wikipedia.org /wiki/Programmed_input/output (1716 words)

	Introduction to VESA programming
		The standard VGA CPU address space for 16 color graphics modes is typically at segment A000h for 64k.
		Super VGAs and their modes require more than the standard 256k bytes of memory but also require that the address space for this memory be restricted to the standard address space for compatibility reasons.
		Every Super VGA hardware implementation provides a mechanism for software to specify the offset from the start of video memory which is to be mapped to the start of the CPU address space.
	www.monstersoft.com /tutorial1/VESA_intro.html (6808 words)

	Patent 4975832: Microcomputer system with dual DMA mode transmissions
		The DMA controller circuit 14 functions to selectively set the microcomputer 10 in the DMA mode such that the data is sent directly between the RAM section of the memory 13 and the I/O device 17, bypassing the CPU 12.
		The efficiency of DMA data transmission is gained, however, at the sacrifice of the response of the CPU, the latter being held isolated from the bus system during the extended period of DMA transmission.
		The DMA controller can cause the CPU either to be electrically coupled to the bus system for programmed CPU data transmission between the I/O device and the memory, or to be uncoupled therefrom for DMA data transmission therebetween.
	www.freepatentsonline.com /4975832.html (6808 words)

	Lloyd Borrett - Computing - Articles - Display Standards, Then and Now
		The VGA is capable of higher display resolution modes such as 720 dot wide by 400 dot high in text modes, or 640 dot wide by 480 dot high in graphics modes.
		Because there was no common standard for these extra modes the card manufacturers would have to provide their own unique software drivers so that these modes could be used with the popular software packages.
		Higher level graphical primitives, like real-time font rendering, circles, arcs, etc., have to be handled by the PC's CPU, which performs the calculations and uses the 8514/A to display the results.
	www.borrett.id.au /computing/art-1990-09-01.htm (1517 words)

	Operand specifier processing (EP0349124B1)
		A method of specifying the operands for a microcoded CPU employs a combination of a set of microinstruction routines for generic operand modes, along with hardware primitives for selecting various specific types of operand treatment.
		Decode of a machine-level instruction produces an entry point for the microstore to select one of the set of generic operand modes, and also decode of the instruction produces control bits that are used directly to select the specific operand type or use by the hardware primitives.
		e) using said selected sequence of microinstructions and said specific control bits in execution and addressing means in said CPU to fetch or select operands to be processed by said instruction in said CPU.
	www.delphion.com /details?pn=EP00349124B1 (352 words)

	Direct Memory Access (DMA) Modes and Bus Mastering DMA
		Bus mastering allows the hard disk and memory to work without relying on the old DMA controller built into the system, or needing any support from the CPU.
		Bus mastering DMA keeps CPU utilization low, which is the amount of work the CPU must do during a transfer.
		As described in the page describing programmed I/O, that method of transferring data between the hard disk and the rest of the system has a serious flaw: it requires a fair bit of overhead, as well as the care and attention of the system's CPU.
	www.storagereview.com /guide2000/ref/hdd/if/ide/modesDMA.html (961 words)

	Linux: Multimon Radio Transmission Decoder
		An arbitrary set of the above modes may run concurrently on the same input signal (provided the CPU power is sufficient), so you do not have to know in advance which mode is used.
		Note however that some modes might require modifications to the radio (especially the 9600 baud FSK and the POCSAG modes) to work properly.
		The multimon software can decode a variety of digital transmission modes commonly found on UHF radio.
	www.baycom.org /~tom/ham/linux/multimon.html (961 words)

	EDN Access -- 09.14.95 EDN's 22nd Annual µP/µC Directory - 32-bit chips
		AMD's 386SC300 chip has four power-saving modes: low speed (CPU goes to 0.5 MHz); doze, which stops CPU, system, and DMA clocks; sleep, which stops additional clocks and peripherals; and suspend, which stops everything except RTC and memory.
		AMD's K5, although software- and pin-compatible with Intel's Pentium, is a unique 586-class CPU.
		The lack of pin compatibility has limited the acceptance of NexGen's product because the CPU has limited chip-set support.
	www.edn.com /archives/1995/091495/19df32bt.htm (6924 words)

	SSLeay 0.9.0b docs
		For more information about the specific RC5 modes in this library (ecb, cbc, cfb and ofb), read the section entitled DES encryption modes overview.
		See the des_encrypt() man page for use of these routines in implementing various encryption modes from the underlying function.
		Don't save or pass around RC5_32_KEYs since they are CPU architecture dependent, the initial data is not.
	www.umich.edu /~x509/ssleay/rc5.html (834 words)

	Mednafen - NES, PC Engine, GB, GBA, Atari Lynx Emulator
		PCE: Altered HuC6280 instruction timing slightly(removed the tests for indirect indexed and indexed indirect addressing modes to use extra CPU cycles).
		PCE: Several CPU cycles are now emulated between setting the in-vblank flag and the vblank IRQ occurring.
		PCE: Increased the number of cpu cycles per scanline from 454 to 455, based on tests I performed.
	mednafen.com (1579 words)

	Addressing mode - Wikipedia, the free encyclopedia
		Addressing modes, a concept from computer science, are an aspect of the instruction set architecture in most central processing unit (CPU) designs.
		The various addressing modes that are defined in a given instruction set architecture define how machine language instructions in that architecture identify the operand (or operands) of each instruction.
		Furthermore, an addressing mode which, in one given architecture, is treated as a single addressing mode may represent functionality that, in another architecture, is covered by two or more addressing modes.
	en.wikipedia.org /wiki/Addressing_mode (2674 words)

	Bus Mastering 950/950A
		The advantage of using the Bus Master DMA is that it uses less CPU resources than PIO and therefore it's of particular benefit in multitasking environments, where the CPU can work on a different program while data is transferred to or from the HDD.
		Also the new Multi Word DMA Modes introduced by the EIDE/Fast ATA specifications are able to transfer data just as fast as the new PIO (Programmed Input/Output) Modes.
		Note: There is a incompatability problem between the Creative Labs SB32 and AWE 64 and the use of the Intel Bus Master Drivers v3.01.
	home.att.net /~BDRM/Software/Windows/c.htm (379 words)

	Olympus MIC-D: Integrated Circuit Gallery - Intel 386 Microprocessor
		The 80386DX is the new name given to the original 386 CPU after the release of the 80386SX, a scaled down version of the best-selling silicon chip.
		The best-selling 386 was the first processor for the personal computer that was able to switch between real and enhanced modes without rebooting.
		The 386 central processing unit (CPU) was originally fabricated at the same 1.5-micron linewidth process level as the 286, but the number of transistors was more than doubled to 275,000.
	www.olympusmicro.com /micd/galleries/chips/intel386a.html (354 words)

	Great Microprocessors of the Past and Present
		The Hitachi SH series was meant to replace the 8-bit and 16-bit H8 microcontrollers, a series of PDP-11-like (or National Semiconductor 32032/32016-like) memory-data CPUs with sixteen 16-bit registers (eight in the H8/300), usable as sixteen 8-bit or combined as eight 32-bit registers (for addressing, except H8/300), with many memory-oriented addressing modes.
		Another CPU, the National Semiconductor PACE, was based on the NOVA design, but featured 16 bit addressing, more addressing modes, and a 10 level stack (like the 8008), but lacked hardware multiply and divide.
		Competing personal computers such as the Amiga and Atari ST, and early workstations by Sun, Apollo, NeXT and most others also used 680x0 CPUs (including one of the earliest workstations, the Tandy TRS-80 Model 16, which used a 68000 CPU and Z-80 for I/O and VM support).
	bwrc.eecs.berkeley.edu /CIC/archive/cpu_history.html (15782 words)

	Data processing system with a microprogrammed dispatcher for working either in native or non-native mode - United States Patent 3,997,895
		The following modes of operation of the CPU are available under control of the CSU 1301; (a) native mode; (b) emulation mode (non-native mode); (c) concurrent native and emulation modes; (d) diagnostic mode.
		In the normal processing mode a hardware error detected in any CPU functional unit will activate a hardware error line (not shown).
		The instructions are stored in a control store array in the control store coupled with the bus, and allows operation of either the ALU (native mode of operation) or the EMU (non-native mode of operation), dependent upon the microprogram's instruction in the control store thereby giving increased efficiency of operation of the system.
	xrint.com /patents/us/3997895 (6604 words)

	Micro Emulator
		Since Addressing Modes are a major key part in CPU codes, those modes are identified and emphasized here for the individual's attention, as they occur.
		The M6800 CPU is a Memory-Mapped I/O Device, rather than a Port-Mapped I/O Device, and these are simulated as well.
		To achieve the M6800 Emulation process, this program examines the given binary code against the parameters expected by a M6800 Processor, and literally spells out the translation of this binary code, based on what it represents to a M6800 Processor, and the action that should be taken.
	www.sfe-dcs.com /Projects/Microprocessor/M6800/M6800.html (6604 words)

	PDP-11
		This latter innovation, together with some of the addressing modes, provided constants, absolute addresses, and relative (position independent) addressing.
		The daisy chain order established the order of the devices at that priority level.) In the case of the PDP-11 design, this meant that the interrupt grant order was determined by how close the physical hardware was to the CPU on the bus.
		The LSI-11 was the first PDP-11 model produced using large-scale integration; the entire CPU was contained on 4 LSI chips.
	www.sciencedaily.com /encyclopedia/pdp_11 (6604 words)

	Motorola 68020 - Wikipedia, the free encyclopedia
		The new addressing modes added another level of indirection to many of the pre-existing modes, and added quite a bit of flexibility to various indexing modes and operations.
		It was, however, extremely uncommon to see more than one CPU or FPU in the same system.
		Most Unix boxes made with 68020s were simply the '020, an FPU (68881 or 68882) and an MMU (68841 or 68851).
	en.wikipedia.org /wiki/68020 (336 words)

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	247-info.dyndns.org /content/motorola-accessory (268 words)

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	NO$CPC
		Advantages: Supports CPC Plus functions, supports 'oversize' video modes, colors and resolution may be changed each scanline, slightly more accurate CPU emulation.
		Disadvantages: No CPC Plus support, display may be split into 5 sections of different colors/modes only, not supporting 'oversize' video modes.
		Advantages: Much faster (working smooth on 33MHz computers), supports VGA, EGA, CGA and Hercules graphics carts, separate versions available optimized for different CPUs, supports XTs and ATs.
	www.work.de /nocash/cpc.htm (174 words)

	XMM SSE2 floating point instructions
		XMMSSE2_CONV: MOV EAX,1 ;request CPU feature flags CPUID ;0Fh, 0A2h CPUID instruction TEST EDX,4000000h ;test bit 26 (SSE2) JNZ >L30 ;SSE2 available CALL NOSSE2FPMESS ;displays message if SSE2 not available RET L30: ;*** display XMM registers in both SSE and SSE2 modes**..
		XMMSSE2_FPDATA: MOV EAX,1 ;request CPU feature flags CPUID ;0Fh, 0A2h CPUID instruction TEST EDX,4000000h ;test bit 26 (SSE2) JNZ >L20 ;SSE2 available CALL NOSSE2FPMESS ;displays message if SSE2 not available RET L20: ;***** display XMM registers in SSE2 mode..
		XMMSSE2_SHUFF: MOV EAX,1 ;request CPU feature flags CPUID ;0Fh, 0A2h CPUID instruction TEST EDX,4000000h ;test bit 26 (SSE2) JNZ >L28 ;SSE2 available CALL NOSSE2FPMESS ;displays message if SSE2 not available RET L28: ;***** display XMM registers in SSE2 mode..
	www.jorgon.freeserve.co.uk /TestbugHelp/XMMfpins2.htm (1037 words)

	SVC Chaos: SNK vs. Capcom - Reader Review - GameFAQs
		Worst Features: Awful roster selection, shoddy controls, fights tend to drag on, unbalanced CPU difficulty, still using KoF '94-quality sprites, lack of variety in modes.
		In addition, the roster is mind-numbingly small (approximately 25 characters as opposed to Capcom VS SNK 2's 44) Moving away from the roster, a lack of modes also hurts the gameplay category.
		No team matches or other SNK-ish modes are here.
	www.gamefaqs.com /console/xbox/review/R90212.html (1037 words)

	Introduction to VESA programming
		In Version 1.2 and later of the VESA Super VGA BIOS Extension, it is recommended that Direct Color modes use the Direct Color MemoryModel and use the MaskSize and FieldPosition fields of the ModeInfoBlock to describe the pixel format.
		In particular, the VESA BIOS is responsible for mapping video memory into the CPU address space while the application is responsible for performing the actual memory read and write operations.
		This combination software and hardware interface is accomplished by informing the application of the parameters that control the hardware mechanism of mapping the video memory into the CPU address space and then letting the application control the mapping within those parameters.
	www.monstersoft.com /tutorial1/VESA_intro.html (6808 words)

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In the News (Thu 24 Dec 09)