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	Pipeline (computer) - Wikipedia, the free encyclopedia
		The elements of a pipeline are often executed in parallel or in time-sliced fashion; in that case, some amount of buffer storage is often inserted between elements.
		Instruction pipelines, such as the classic RISC pipeline, which are used in processors to allow the parallel execution of two or more consecutive instructions from a nominally sequential stream; the processing elements are the logical circuits that implement the various stages of an instruction (address decoding and arithmetic, register fetching, cache lookup, etc.).
		Software pipelines, consisting of multiple processes arranged so that the output stream of one process is automatically and promptly fed as the input stream of the next one.
	en.wikipedia.org /wiki/CPU_pipeline (567 words)

	System and method for recording sufficient data from parallel execution stages in a central processing unit for ...
		Fault recovery of a pipelined CPU is more complex, because the execution of instruction N+1 (and perhaps even N+2) may or may not be postponed by the occurrence of a fault in instruction N. This scenario is illustrated in FIG.
		In general, the execution pipeline history queue 738 is the key to understanding the CPU instructions that were in progress at the time of the fault.
		Execution pipeline history queue 738, along with the bus node arbiter 704 queues allow the machine to be stopped after any processor cycle, and the exact state of the machine can be determined in terms of the execution and memory access stages of instruction, along with correlating information about asynchronous DMA operations to memory.
	www.freepatentsonline.com /5649088.html (7950 words)

	Classic RISC pipeline - Wikipedia, the free encyclopedia
		The rest of the pipeline was free to continue execution while the multiply/divide unit did its work.
		Each multiplexor selects between a register file read port, the current register pipeline of the ALU, and the current register pipeline of the access stage (which is either a loaded value or a forwarded ALU result).
		The classic RISC pipeline resolves branches in the Decode stage, which means the branch resolution recurrence is two cycles long.
	en.wikipedia.org /wiki/Classic_RISC_pipeline (2843 words)

	4.4 Basic CPU Design
		CPUs based on microcode contain a small, very fast, execution unit that fetches instructions from the microcode bank (which is really nothing more than fast ROM on the CPU chip).
		The CPU is attempting to fetch the next byte from the prefetch queue for use as an operand, at the same time it is fetching operand data from the prefetch queue for use as an opcode.
		In a standard superscalar CPU it is the programmer's (or compiler's) responsibility to schedule (arrange) the instructions to avoid hazards and pipeline stalls.
	webster.cs.ucr.edu /AoA/Windows/HTML/CPUArchitecturea3.html (13546 words)

	Athlon64 and General CPU Technology mini-refrence - Overclockers Forums
		A pipeline is a list of instructions that the cpu is working on - if the first-most instruction is an add or something, the cpu can look further down the pipeline for a memory load and start working on that, since it can both add and load from memory at the same time.
		Pipeline stalls, or bubbles, reduce a pipeline's average instruction throughput, because they prevent the pipeline from attaining the maximum throughput of one finished instruction per cycle.This is the problem with Intel's CPU's.
		This is because you need to keep the pipeline fed, and more importantly if you have a branch prediction miss and you have to throw away data or you have an error in calculating data and you have to throw the data away you're loosing more work cycles than on a shorter pipeline processor.
	www.ocforums.com /showthread.php?t=387353 (10459 words)

	Art of Assembly: Chapter Three-5
		The CPU is attempting to fetch the next byte from the prefetch queue for use as an operand, at the same time it is fetching 16 bits from the prefetch queue for use as an opcode.
		At T=T6 the CPU completes the execution of the first instruction, computes the result for the second, etc., and, finally, fetches the opcode for the sixth instruction in the pipeline.
		The CPU uses the data/address bus only when reading a value which is not in the cache or when flushing data back to main memory.
	webster.cs.ucr.edu /AoA/DOS/ch03/CH03-5.html (2923 words)

	Central processing unit for processing a plurality of threads using dedicated general purpose registers and masque ...
		The pipeline controller, the scheduler, the events system, and the masquerade registers facilitate the implementation and execution of the methods of the present invention such as efficient thread scheduling, branch delays, elimination of delay slots after stores that provide further increases in the performance and bandwidth.
		Pipeline Control uses specialized methods including low-latency thread switching, a method for scheduling threads, elimination of pipeline stalls or pipeline flushing, predictable branch delays, a forwarding method to eliminate delay slots after store instructions, and a method for efficiently scheduling the cpu buses.
		This means that the cpu (24) can be executing in one thread while at the same time moving data by means of one of the bus engines (220 and 222) into the same or a different general purpose register set (210), or other storage space such as local data memory (106) for example.
	www.freepatentsonline.com /5524250.html (8174 words)

	ASIC design flow gives CPU core custom performance
		The instruction-fetch portion of the pipeline (the IFU) is coupled to the execution portion of the pipeline (the IDU, OFU, and EXU) via a 12-byte Instruction Fetch Buffer (IFB).
		The key is that the same hardware register remains allocated to a particular instruction's result throughout its lifetime in the pipeline despite the result apparently being moved between A, B, and C by subsequent instructions pushing and popping the architectural register-stack.
		Since the cache is single-ported, this would cause the CPU pipeline to stall, even though on average the cache controller is capable of dealing with the full read/write bandwidth.
	www.us.design-reuse.com /articles/article3761.html (3333 words)

	NeXT and Sun, SPIM simulator
		Describe the implementation of the CPU shown in diagram 3.
		Consider the pipeline and multicycle architectures studied in class.
		Assume that for the pipeline architecture, a branch not taken incurs no penalty but a branch taken incurs a three cycle stall, and that data forwarding resolves all data hazards, except when the instruction following a load word depends on the data loaded, in which case a one cycle stall occurs.
	cs.colgate.edu /faculty/nevison/cs201web/lectureNotes/finalexam.htm (936 words)

	Dr. Dobb's \| How to accelerate algorithms by automatically generating FPGA coprocessors \| August 9, 2006
		CPU Bus Connected: Processor bus-connected accelerators require the CPU to move data and send commands through a bus.
		Being coupled to the instruction pipeline, instructions not recognized by the CPU can be executed by the coprocessor.
		Instructions from cache or memory are simultaneously presented to the CPU decoder and the APU controller.
	www.ddj.com /dept/embedded/191901647 (1409 words)

	Ars Technica: Understanding Pipelining and Superscalar Execution - Page 6 - (12/2002) (Site not responding. Last check: 2007-10-15)
		This version shows all four "stages" of the basic pipeline, but with the twist that the number of actual pipeline stages in the execute "stage" (or execute phase) varies depending on the particular execution unit.
		Both pipelined and superscalar execution are ways of enlarging the processor's "window" on the code stream.
		Both superscalar and pipelined execution are in some sense both forms of parallel execution.
	arstechnica.com /paedia/c/cpu/part-2/cpu2-6.html (977 words)

	How a CPU Works \| Hardware Secrets
		In the past, the CPU controlled the data transfer between the hard disk drive and the RAM memory.
		Since the hard disk drive is slower than the RAM memory, this slowed down the system, since the CPU would be busy until all the data was transferred from the hard disk drive to the RAM memory.
		This means that for these processors the CPU accesses the RAM memory directly, without using the north bridge chip shown on Figure 1.
	www.hardwaresecrets.com /article/209 (608 words)

	Paul Hsieh's 7th generation x86 CPU Comparisons
		The Athlon is a long pipelined architecture, and like the P6, does a lot of work to unravel some of the oddball conventions of the x86 instruction architecture in order to feed a powerful RISC-like engine.
		The 21264 pipeline is structured with a maximum of 2 memory, integer, or FP instructions, from which any combination of executing 4 can be sustained per clock.
		Apparently they have fully pipelined the FMUL though which is an improvement versus the P6 core (and it has the same 5 clock latency).
	www.azillionmonkeys.com /qed/cpujihad.shtml (7931 words)

	CPUs > Dream Machine 2004 Contender (Site not responding. Last check: 2007-10-15)
		During each clock cycle, the CPU can retire the results of one instruction at the end of the pipeline while fetching a new instruction into the front of the pipeline.
		Figure 3.3 The classic 32-bit Athlon XP CPU was the budget workhorse for several years, but it's fallen by the wayside with the introduction of newer 64-bit Athlons.
		Figure 3.4 The Celeron CPU is a basic Pentium 4 core, but the performance is severely limited by its tiny 128KB L2 cache.
	www.quepublishing.com /articles/article.asp?p=339473 (4742 words)

	Paul Hsieh's 6th generation x86 CPU Comparisons
		These are all MMX capable 6th generation x86 compatible CPUs, however I am not going to discuss the MMX capabilities at all beyond saying that they all appear to have similar functionality.
		The execution stages perform in one or two pipelined stages (with the exception of the floating point unit which is not pipelined, or complex instructions which stall those units during execution.) In theory, all units can be executing at once.
		The primary microarchitecture difference of the 6x86MX CPU versus the K6 and P-II CPUs is that it still does native x86 execution rather than translation to internal RISC ops.
	www.azillionmonkeys.com /qed/cpuwar.html (11012 words)

	CPU Pipeline Experiments Lab Lab #2
		To understand the workings of a modern CPU, concentrating on the use of the pipeline and it's effects on branch prediction, and to see how data dependencies and control dependencies affect the performance of a program running on the MCF5407.
		In this lab you will be conducting experiments on the CPU pipeline of the Motorola MCF5407 microprocessor.
		This creates a data dependency in D1 on the pipeline such that the processor would have to wait for the new value of D1 to be written back from the execution of the first instruction before it can execute the second instruction.
	www.ele.uri.edu /courses/ele408/lab2.html (757 words)

	Developer Pipeline \| Researcher: CPU No-Execute Bit Is No Big Security Deal
		Researcher: CPU No-Execute Bit Is No Big Security Deal
		The no-execute feature that's been folded in the newest processors to ward off malicious attacks isn't the panacea that many users think it is, a security researcher at the Black Hat conference claimed in his presentation Wednesday.
		Learn how online backup and recovery can protect your business-critical server data from disaster.
	www.developerpipeline.com /166403759?cid=RSSfeed (783 words)

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