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Topic: Cache algorithms

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	Cache-Control
		Cache directives are unidirectional in that the presence of a directive in a request does not imply that the same directive is to be given in the response.
		Cache directives MUST be passed through by a proxy or gateway application, regardless of their significance to that application, since the directives might be applicable to all recipients along the request/response chain.
		If a cache returns a stale response, either because of a max-stale directive on a request, or because the cache is configured to override the expiration time of a response, the cache MUST attach a Warning header to the stale response, using Warning 110 (Response is stale).
	www.ieinspector.com /httpanalyzer/manual/process128.htm (2979 words)

	DEFER Cache Algorithms
		Further, clean blocks are not affected by the logging algorithms and hence read performance of clean blocks is as good as that of any other read optimized cooperative caching algorithm.
		When a workstation receives a write request, it writes one copy of the data to its local cache and then forwards a copy to a remote host (it might be a peer or the server depending on the logging algorithm used).
		Cache blocks that are logged to the disk are kept in the remote cache for up to 17#17 seconds before being logged to capture temporal locality.
	www.ececs.uc.edu /~srao/research/thesis/node19.html (818 words)

	Cache - Wikipedia, the free encyclopedia
		In computer science, a cache (pronounced /kæʃ/, like the English word cash) is a collection of data duplicating original values stored elsewhere or computed earlier, where the original data is expensive (usually in terms of access time) to fetch or compute relative to reading the cache.
		Caches have proven extremely effective in many areas of computing because access patterns in typical computer applications have locality of reference.
		The cache of disk sectors in main memory is usually managed by the operating system kernel or file system.
	en.wikipedia.org /wiki/Cache (1845 words)

	HTTP/1.1: Caching in HTTP
		While the origin server (and to a lesser extent, intermediate caches, by their contribution to the age of a response) are the primary source of expiration information, in some cases the client might need to control a cache's decision about whether to return a cached response without validating it.
		Cache entries might persist for arbitrarily long periods, regardless of expiration times, so it might be inappropriate to expect that a cache will never again attempt to validate an entry using a validator that it obtained at some point in the past.
		If a new cacheable (see sections 14.9.2, 13.2.5, 13.2.6 and 13.8) response is received from a resource while any existing responses for the same resource are cached, the cache SHOULD use the new response to reply to the current request.
	www.w3.org /Protocols/rfc2616/rfc2616-sec13.html (8003 words)

	Cache algorithms - Wikipedia, the free encyclopedia
		Cache algorithms are optimizing instructions – algorithms – that a computer program can follow to manage a cache of information stored on the computer.
		Cache size is usually limited, and if the cache is full, the computer (that is, the programmer) must decide which items to keep and which to discard to make room for new items.
		Belady's Min – The most efficient caching algorithm would be to always discard the information that will not be needed for the longest time in the future.
	en.wikipedia.org /wiki/Cache_algorithms (325 words)

	Cilk Abstract (Site not responding. Last check: )
		Unlike previous optimal algorithms, these algorithms are cache oblivious: no variables dependent on hardware parameters, such as cache size and cache-line length, need to be tuned to achieve optimality.
		For a cache with size Z and cache-line length L where Z=\Omega(L^2) the number of cache misses for an m\times n matrix transpose is \Theta(1+mn/L).
		Algorithms developed for these earlier models are perforce cache-aware: their behavior varies as a function of hardware-dependent parameters which must be tuned to attain optimality.
	supertech.lcs.mit.edu /cilk/papers/abstracts/abstract4.html (260 words)

	Hardware Cache Cohierence
		In addition to handling cache hit and miss events, local processors must be able to generate, broadcast and respond to special signals, or consistency commands, that are used to send special instructions to remote caches for the purposes of implementing the coherence protocol.
		The four bus-based cache coherence algorithms discussed in the remainder of this section will be presented with respect to how they handle cache hit and miss situations along with, when they generate, and how they respond to consistency signals.
		Cache 4 has a copy present, but it is invalid, indicating that it is stale and might be inconsistent with the current copy.
	www.cs.drexel.edu /~bmitchel/research/CacheCoherence/CacheCoherence.html (8155 words)

	A Unified Algorithm for Cache Replacement and Consistency in Web Proxy Servers - Shim, Scheuermann, Vingralek ...
		Cache replacement algorithms play a central role in the response time reduction by selecting a subset of documents for caching so that an appropriate performance metric is maximized.
		Cache consistency algorithms enforce appropriate guarantees about the staleness of documents it stores.
		suggests a unified algorithm for cache replacement and consistency.
	citeseer.ist.psu.edu /shim98unified.html (686 words)

	Implementation of Optimized Cache Replenishment Algorithms in a Soft Caching System
		Proxy caches, or intermediate network nodes in which frequently used data are stored, emerge as an efficient solution to reduce network traffic.
		In [7], two soft caching scenarios are distinguished, namely, (i) hard access, in which the user always requires the entire image, and (ii) soft access, in which she can possibly choose to view the image at a certain resolution level.
		In [9] efficient low-complexity algorithms to optimize the management of a soft cache are proposed.
	sipi.usc.edu /~ortega/SoftCaching/MMSP98 (2842 words)

	Developing for Developers : Cache-oblivious data structures
		In most data structure and algorithms classes, the model used for basic analysis is the traditional RAM model: we assume that we have a large, random-access array of memory, and count the number of simple reads/writes needed to perform the algorithm.
		It is possible to design data structures that specifically take advantage of the cache line size B. For example, in a previous post I described an unrolled linked list data structure where each node fills up a cache line, achieving similar cache performance to arrays while still allowing efficient insertions and deletions.
		This is the theoretical benefit of cache-oblivious algorithms: we can reason about the algorithm using a very simple two-level cache model, and it automatically generalizes to a complex, deep cache hierarchy with no additional work.
	blogs.msdn.com /devdev/archive/2007/06/12/cache-oblivious-data-structures.aspx (3096 words)

	Cache Policy and Management for Devices
		The default recommended cache algorithm is to save the newest content, and throw away the oldest content, when the cache becomes full.
		The default algorithm is to throw away the oldest content from the gadgets that are over their limit, although the gadget itself may recommend using different criteria.
		The cache algorithm that is requested by the gadget is passed to the device in the ISideShowDriver::OnAddApplication method as the CacheAlgorithm parameter.
	msdn.microsoft.com /en-us/library/aa939010.aspx (517 words)

	Existing Document Replacement Algorithms
		We describe nine cache replacement algorithms proposed in recent studies, which attempt to minimize various cost metrics, such as miss ratio, byte miss ratio, average latency, and total cost.
		In describing the various algorithms, it is convenient to view each request for a document as being satisfied in the following way: the algorithm brings the newly requested document into the cache and then evicts documents until the capacity of the cache is no longer exceeded.
		Algorithms are then distinguished by how they choose which documents to evict.
	www.usenix.org /publications/library/proceedings/usits97/full_papers/cao/cao_html/node4.html (755 words)

	Competitive analysis of the LRFU paging algorithm 1
		The algorithm decides which page to evict when a request arrives for a page which is not presently in the cache and the cache is full.
		The state of the cache at the end of each k-phase is isomorphic to the state of the cache at the beginning of the phase.
		Now, the state of cache at the end of the second phase is similar to its state at the end of the first phase.
	www.research.att.com /~edith/Papers/HTML/wads01/index.html (2003 words)

	Abstract
		For a cache with size Z and cache-line length L where Z=\Omega(L^2) the number of cache misses for an m\times n matrix transpose is \Theta(1+mn/L).
		We introduce an ``ideal-cache'' model to analyze our algorithms, and we prove that an optimal cache-oblivious algorithm designed for two levels of memory is also optimal for multiple levels.
		Algorithms developed for these earlier models are perforce cache-aware: their behavior varies as a function of hardware-dependent parameters which must be tuned to attain optimality.
	www.fftw.org /~athena/abstracts/abstract9.html (252 words)

	Related Work
		The reason is that in the OS context, the global replacement algorithm is used for stealing memory from idle workstations (i.e.
		Thus, while simple cache sharing performs poorly in the OS context, it suffices for Web proxy cache sharing as long as each proxy's resource configuration is appropriate for its load.
		Finally, note that the technique of Bloom filter based summary cache is not restricted to the Web proxy caching context, but can be used where-ever the knowledge of other caches' contents is beneficial, for example, in caching and load-balancing in clustered servers.
	pages.cs.wisc.edu /~cao/papers/summary-cache/node16.html (781 words)

	The InveStore Default Cache Write Algorithms (Site not responding. Last check: )
		The algorithm delays writes to optical disk, flushing files in the background at a later time.
		With Lazy Write, InveStore writes data from the RAM cache to optical disk in a contiguous thread that is more efficient for throughput and significantly reduces file system overhead.
		If an InveStore user encounters any PC sub-system or jukebox hardware problems, it is recommended that the Default Cache Write Algorithm be changed to Write Through until the PC or jukebox problems are resolved and stable operation of the optical server is insured.
	www.pegasus-afs.com /eSupport/cache_algorithms.htm (569 words)

	Cache-efficient Algorithms and Data Structures: Theory and Experimental Evaluation
		The ideal-cache model is an abstraction of the memory hierarchy in modern computers which facilitates the design of algorithms that can use the caches (i.e., memory levels) in the hierarchy efficiently without using the knowledge of cache parameters.
		These algorithms are useful both in applications that work on massive datasets and in applications that run on small-memory systems such as handheld devices.
		In the area of graph algorithms and data structures, we introduce the first efficient cache-oblivious priority queue supporting Decrease-Key operations, and use it to obtain the first non-trivial cache-oblivious single-source shortest path algorithms for both directed and undirected graphs with general non-negative edge-weights.
	www.cs.utexas.edu /~shaikat/papers/dissertation.html (478 words)

	Home Page
		Despite the well-known interactions between prefetching and caching, almost all buffer cache replacement algorithms have been proposed and studied comparatively without taking into account file system prefetching which exists in all modern operating systems.
		The complexity of interactions between such subsystems entails that the various buffer caching algorithms are comparatively studied in a realistic setting.
		In addition, even with such a kernel implementation, it is often non-trivial to obtain a controlled environment, e.g., a fixed cache size in the presence of a unified buffer cache, in the actual kernel for comparing various algorithms on an even basis.
	cobweb.ecn.purdue.edu /~ychu/accusim (888 words)

	ANALYSIS OF CACHE REPLACEMENT-ALGORITHMS
		The model identifies a set of lines in the LRU cache that are dead, that is, lines that must leave the cache before they can be rereferenced.
		The model shows that the majority of the cache misses that OPT avoids over LRU come from the most-recently-discarded lines of the LRU cache.
		Simulation results, using a trace-tape and cache simulator, show that these new algorithms achieve up to eight percent fewer misses than LRU and obtain about 20 percent of the miss reduction that OPT obtains.
	scholarworks.umass.edu /dissertations/AAI8509594 (211 words)

	DerbyLruCacheManager - Db-derby Wiki
		The problem stated is that the existing replacement algorithm performs poorly so we need to research new algorithms for page replacement and implement it in Apache Derby.
		The PluggableCache is my attempt to separate the cache implementation from the replacement policy.
		What I did was to maintain the cache's metadata separately in accordance to the replacement policy (an instantiation of an replacement policy is called a replacement policy engine).
	wiki.apache.org /db-derby/DerbyLruCacheManager (918 words)

	CS262A Reading Summary
		Transactional cache consistency algorithms are closely related to but quite different from distributed shared memory cache cosistency algorithms.
		Detection-based algorithms allow stale data in local caches and need to validate them when committing transactions.
		However, this aspect of the algorithms is orthogonal to whether the algorithm is pessimistic or optimistic, i.e.
	www.cs.berkeley.edu /~zf/cs262b/tx_cache_consistency.htm (297 words)

	Cache-Oblivious Algorithms in Practice
		The main idea behind cache-oblivious algorithms is to achieve optimal use of caches on all levels of a memory hierarchy without knowledge of their size.
		Our results show, that for the cache-oblivious algorithms used in our case-study, the extra work incurred by making algorithms cache oblivious is too big, for them to be competitive on all levels in the memory hiearchy.
		Cache-obliviousalgorithms do outperform traditional RAM-model algorithms when working on data sets larger than main memory, but in the lower levels of the memory hierarchy, the traditional RAM-based algorithms are faster, due to a smaller amount of work.
	www.dunkel.dk /thesis (440 words)

	Adaptive Algorithms for Cache-efficient Trie Search
		The choice of the data structure depends on cache characteristics as well as the fanout of the node.
		Third, the size and the layout of individual data structures is determined based on the size of the symbols in the alphabet as well as characteristics of the cache(s).
		A comparison of the number of instructions executed indicates that these algorithms derive their performance advantage primarily by making better use of the memory hierarchy.
	www.cs.ucsb.edu /~acha/publications/soda98-submitted.html (162 words)

	Performance Research, Part 2: Browser Cache Usage - Exposed! » Yahoo! User Interface Blog
		An “empty cache” means the browser bypasses the disk cache and has to request all the components to load the page.
		A “full cache” means all (or at least most) of the components are found in the disk cache and the corresponding HTTP requests are avoided.
		The main reason for an empty cache page view is because the user is visiting the page for the first time and the browser has to download all the components to load the page.
	yuiblog.com /blog/2007/01/04/performance-research-part-2 (5314 words)

	MIT CSAIL Research Abstracts
		In this research, we have developed optimal cache-aware and cache-oblivious algorithms for matrix-vector multiplication of sparse matrices derived from well-shaped meshes.
		The key problem is to lay out the mesh to minimize cache misses.
		If n is the graph size, B is the cache block size, and M is the size of cache, and d is the dimensionality of the geometric domain of the mesh then an optimal layout allows the matrix-vector multiplication to run in O(n/B) memory transfers in the cache-oblivious model.
	publications.csail.mit.edu /abstracts/abstracts06/bradley3/bradley3.html (329 words)

	Cache-Oblivious Algorithms (Extended Abstract) (ResearchIndex)
		Abstract: This paper presents asymptotically optimal algorithms for rectangular matrix transpose, FFT, and sorting on computers with multiple levels of caching.
		Unlike previous optimal algorithms, these algorithms are cache oblivious: no variables dependent on hardware parameters, such as cache size and cache-line length, need to be tuned to achieve optimality.
		Nevertheless, these algorithms use an optimal amount of work and move data optimally among multiple levels of cache.
	citeseer.ist.psu.edu /307799.html (652 words)

	Cache-Oblivious Algorithms - Prokop (ResearchIndex)
		Abstract: This thesis presents "cache-oblivious" algorithms that use asymptotically optimal amounts of work, and move data asymptotically optimally among multiple levels of cache.
		An algorithm is cache oblivious if no program variables dependent on hardware configuration parameters, such as cache size and cache-line length need to be tuned to minimize the number of cache misses.
		The rationale for this approach is that if the computation at a particular level of recursion doesn t fit into some level of the...
	citeseer.ist.psu.edu /prokop99cacheobliviou.html (856 words)

	Erik D. Demaine: Cache-Oblivious Algorithms and Data Structures
		Erik D. Demaine, “Cache-Oblivious Algorithms and Data Structures”, in Lecture Notes from the EEF Summer School on Massive Data Sets, Lecture Notes in Computer Science, BRICS, University of Aarhus, Denmark, June 27–July 1, 2002, to appear.
		A recent direction in the design of cache-efficient and disk-efficient algorithms and data structures is the notion of cache obliviousness, introduced by Frigo, Leiserson, Prokop, and Ramachandran in 1999.
		Cache-oblivious algorithms perform well on a multilevel memory hierarchy without knowing any parameters of the hierarchy, only knowing the existence of a hierarchy.
	erikdemaine.org /papers/BRICS2002 (218 words)

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