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	Cache coherency - Wikipedia, the free encyclopedia
		Cache coherence is a special case of memory coherence.
		Cache coherence is intended to manage such conflicts and maintain consistency between cache and memory.
		Snarfing is where a cache controller watches both address and data in an attempt to update its own copy of a memory location when a second master modifies a location in main memory.
	en.wikipedia.org /wiki/Cache_coherency (381 words)

	What is cache coherence? - A Word Definition From the Webopedia Computer Dictionary
		A memory cache, sometimes called a cache store or RAM cache, is a portion of memory made of high-speed static RAM (SRAM) instead of the slower and cheaper dynamic RAM (DRAM) used for main memory.
		When multiple processors with separate caches share a common memory, it is necessary to keep the caches in a state of coherence by ensuring that any shared operand that is changed in any cache is changed throughout the entire system.
		In a snooping system, all caches on the bus monitor (or snoop) the bus to determine if they have a copy of the block of data that is requested on the bus.
	www.webopedia.com /TERM/C/cache_coherence.html (400 words)

	MIT - Alewife
		Caches enhance the performance of multiprocessors by reducing network traffic and average memory access latency.
		In parallel computing, the problem of cache coherence arises because multiple processors may be reading and modifying the same memory blocks within their own cache.
		When one cache has a block in Read-Write state and another cache requests read privileges for that block, the CMMU sends an update request to the cache that owns the data.
	www.cs.nmsu.edu /~jdage/cs573/cache.html (1367 words)

	Coherence - Wikipedia, the free encyclopedia
		Coherence is an attribute of physical quantities that can be described in terms of waves when a well-defined wavefront can be defined, as in classical optics.
		Cache coherence and (more generally) memory coherence are concepts in computer architecture.
		Coherence can be a cognitive aim in itself or it can be a means by which other cognitive aims such as truth, justification, decision-making, explanation, planning, etc. are achieved.
	en.wikipedia.org /wiki/Coherence (227 words)

	WebFS: A Cache Coherent Global File System
		Cache Coherence: The weak coherency guarantees available in the Internet is sufficient for Web surfing; if the most up to date information is needed, the user simply clicks the reload button.
		Cache coherence is currently under investigation by a number of groups[8,18].
		In the future, we hope to allow for application programmers to develop their own coherence policies if none of the provided techniques are appropriate (such a technique has been explored in other contexts[5,6]).
	www.cs.duke.edu /~vahdat/webfs/webfs.html (4996 words)

	Cache Coherence Issues for Real-Time Multiprocessing
		The simplest cache coherence scheme is the use of a write-through protocol.
		Modified data is kept in the caches, and memory reads are monitored to detect access requests of data that is in one of the caches.
		On copy-back caches, all operations are normally on a cache line basis, which is bursted between the cache and memory.
	www.embedded.com /97/feat9702.htm (3454 words)

	Cache Coherence
		Station-level coherence for a given cache line is enforced between the processor caches and the home memory on the same station or between the processor caches and the network cache on the same station if the home memory of the cache line is a remote station.
		In the network cache the state of the cache line is changed to GV and the processor mask is set to indicate the requesting processor.
		Finally, the NUMAchine cache coherence protocol is conducive to low-cost implementation in hardware, because the amount of memory required for the directories is small and the logic circuitry needed to manipulate those directories is reasonable.
	www.eecg.toronto.edu /EECG/RESEARCH/ParallelSys/numachin.hier/node5.html (2521 words)

	Web Cache Coherence (Site not responding. Last check: 2007-11-05)
		Cache C will set the expiration time for the document to October 13; if the page is requested from cache C on October 12, then C will not check to see whether the page has changed, and the returned page will have a staleness of 4 days.
		In a cache hierarchy all caches contribute together to generate a high hit rate for the user; each cache only receives the pages which lower-level caches did not have, and so its hit rate will only represent the pages which are serviced at a given level of the cache hierarchy.
		We appeal to Web cache researchers who have log data for large caches to make their data publicly accessible so that other researchers can run simulations with those logs; in those logs, IP numbers of host computers can be scrambled if there are privacy concerns.
	www.cs.ubc.ca /local/reading/proceedings/www5/www395/overview.htm (7833 words)

	Optimizing Software Cache-coherent Cluster Architectures
		With the forwarding logic, every cache miss or communication primitive uses only the protocol engine of the home node, thus improving performance in two ways: First, the inter-cluster miss latency is reduced by lessening the number of cycles spent on message passing; and, second there is less contention on the protocol processor.
		The primitives, summarized along with their semantics in Table 1, give to the user some of the advantageous features of asynchronous message-passing, such as non-blocking operations, while retaining the simplicity of the cache coherent shared-memory paradigm, i.e., global cache coherence is maintained.
		The use of programmable protocol processors and of software cache coherence opens a promising and flexible avenue in the implementation of fine-grained, SMP cluster based, shared-memory systems at the cost of a higher protocol processing overhead.
	www.cs.washington.edu /homes/baer/sc.html (3757 words)

	Cache Coherence in Distributed Systems - Kent (ResearchIndex) (Site not responding. Last check: 2007-11-05)
		This document uses CoBlitz to cache paper downloads.
		Most modern computer systems include a hardware cache between the processor and main memory, and many operating systems include a software cache between the file system routines and the disk hardware.
		Kent, Cache Coherence in Distributed Systems, Phd Thesis, Purdue University, 1986.
	citeseer.ist.psu.edu /kent87cache.html (1096 words)

	Querying the Cache - Coherence 3.2 User Guide - Tangosol Coherence Knowledge Base (via CobWeb/3.1 ... (Site not responding. Last check: 2007-11-05)
		When using a Near cache in front of a Partitioned cache, the query execution is similar, except that the value portion of each entry in the result set will be retrieved from the front (local) cache if available.
		The Partitioned Cache implements this method using the Parallel Query feature, which is only available in Coherence Application Edition or higher.
		This method is only intended as a hint to the cache implementation, and as such it may be ignored by the cache if indexes are not supported or if the desired index (or a similar index) already exists.
	wiki.tangosol.com.cob-web.org:8888 /display/COH32UG/Querying+the+Cache (1196 words)

	Fragment Reconstruction: Providing Global Cache Coherence in a Transactional Storage System - Adya, Castro, Liskov, ... (Site not responding. Last check: 2007-11-05)
		Abstract: Cooperative caching is a promising technique to avoid the increasingly formidable disk bottleneck problem in distributed storage systems; it reduces the number of disk accesses by servicing client cache misses from the caches of other clients.
		In this paper, we describe a new storage system architecture, split caching, and a new cache coherence protocol, fragment reconstruction, that...
		Nevertheless, current cooperative caching techniques work only in environments when machines trust one other, a requirement that is...
	citeseer.ist.psu.edu /adya97fragment.html (666 words)

	The Cache Coherence Problem in Shared-Memory Multiprocessors: Software Solutions:0818670967:Igor Tartalja; Veljko ...
		Almost all software solutions are developed through academic research and implemented only in prototype machines, thus leaving the field of software techniques for maintaining the cache coherence widely open for new research and development.
		This book is a collection of all representative approaches to software coherence maintenance and includes a number of related studies in the performance evaluation field.
		In addition, it is a software coherence reference handbook for advanced undergraduate and typical graduate students in multiprocessing and multiprogramming areas.
	www.ecampus.com /bk_detail.asp?isbn=0818670967 (593 words)

	[No title] (Site not responding. Last check: 2007-11-05)
		Snooper of cache which has a MainCache request outstanding cannot respond to MC queries for other outstanding requests.
		When transitioning to a Modified state, a cache will change all other values of data in memory and other caches to OLD Global access to data here strictly a part of verification effort, not algorithm.
		Snooper of cache which has a MainCache request outstanding cannot respond to MC queries for other outstanding requests (due to locked cacheline).
	www.ece.utexas.edu /~doron/cache.ppt (1259 words)

	hibernate.org - Using Tangosol Coherence Cache (Site not responding. Last check: 2007-11-05)
		If you want to be able to explore the cache, and be able to delete some entries selectively from the cache, here are some modifications that can be made to the above clases to enable this functionality.
		These modifications allow one to explore and control the cache in a fairly cache-agnostic way, so this may be useful for other cache provider implementations as well.
		To report statistics on cache usage, we add a CacheStatistics implementation as a member variable into the CoherenceCache implementation, which is updated every time we do a get or put, so we can calculate things like cache hit ratios.
	www.hibernate.org /132.html (491 words)

	CPSC 513 Simple MSI Cache Coherence Protocol (Site not responding. Last check: 2007-11-05)
		This is a directory-based cache coherence protocol, as we discussed in class.
		In order to avoid trying to model a real cache (with tag bits and replacement policies, etc.), we give each processor a cache big enough to hold all of memory.
		The ``Sender Cached'' column tests whether the sender of this message is currently listed in the directory as having the address cached.
	www.cs.ubc.ca /spider/ajh/courses/cpsc513/assign_msicache/protocol.html (926 words)

	cache coherence - a definition from Whatis.com (Site not responding. Last check: 2007-11-05)
		with a separate cache memory for each processor, it is possible to have many copies of any one instruction operand: one copy in the main memory and one in each cache memory.
		When one copy of an operand is changed, the other copies of the operand must be changed also.
		Cache coherence is the discipline that ensures that changes in the values of shared operands are propagated throughout the system in a timely fashion.
	whatis.techtarget.com /definition/0,,sid9_gci211729,00.html (229 words)

	SMPCache English
		Some of the parameters that they can study with the simulator are: Program locality; influence of the number of processors, cache coherence protocols, schemes for bus arbitration, mapping, replacement policies, cache size (blocks in cache), number of cache sets (for set associative caches), number of words by block (memory block size), word wide,...
		In conclusion, the use of the simulator is an innovation in the practical classes that produces an improvement of the quality in education.
		After analysing the basic algorithms and concepts that are present in every cache memory system (uniprocessor or multiprocessor), you could study some theoretical issues related with multiprocessor systems (cache coherence protocols, influence of the number of processors, etc.).
	arco.unex.es /smpcache (2124 words)

	Bandwidth-adaptive, hybrid, cache-coherence protocol (US6883070)
		The switching is according to the activity on the communication network used by the cache coherence messages.
		(b) providing a mechanism for communication of cache coherence messages directly from a given processor unit to a directory and then to at least one other processor unit when indicated by the directory;
		(d) for a given cache coherence message, selecting one the mechanism of step (a) or the mechanism of step (b) based on the evaluation of step (c).
	www.delphion.com /details?pn=US06883070__ (381 words)

	Discussion of cache coherence protocol implementation (Site not responding. Last check: 2007-11-05)
		In the MSI system, an explicit upgrade message is required for a read followed by a write, even if there are no other sharers.
		However, our MESI implementation requires a message to be sent to the directory on elimination of an exclusive line from the L2 cache.
		Some available MESI implementations avoid this replacement message; however, in such systems, the write-back of a modified line requires an acknowledgment from the memory controller and holds an entry in the write-back buffer until the reply arrives [12].
	www-ece.rice.edu /~rsim/Manual/node109.html (158 words)

	Performance of Cache Coherence in Stackable Filing
		Individual layers of such a system often need to cache data to improve performance or provide desired functionality.
		Without a cache coherence solution, layer designers must either restrict layer access and flexibility or compromise the layered structure to avoid potential data corruption.
		This paper presents a general cache coherence architecture for stackable filing, including a standard approach to data identification as a key component to layered coherence protocols.
	www.isi.edu /~johnh/PAPERS/Heidemann95c.html (326 words)

	LimitLESS Directories: A Scalable Cache Coherence Scheme - Chaiken, Kubiatowicz, Agarwal (ResearchIndex) (Site not responding. Last check: 2007-11-05)
		Abstract: Caches enhance the performance of multiprocessors by reducing network traffic and average memory access latency.
		32: The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor (context) - Lenoski, Laudon et al.
		43 Software-Controlled Caches in the VMP Multiprocessor (context) - Cheriton, Slavenberg et al.
	citeseer.ist.psu.edu /111919.html (649 words)

	An Adaptive Cache Coherence Protocol Specification for Parallel Input/Output Systems (Site not responding. Last check: 2007-11-05)
		Caching has been intensively used in memory and traditional file systems to improve system performance.
		However, the use of caching in parallel file systems and I/O libraries has been limited to I/O nodes to avoid cache coherence problems.
		The cache coherence problem is solved by using a dynamic scheme of cache coherence protocols with different sizes and shapes of granularity.
	doi.ieeecomputersociety.org /10.1109/TPDS.2004.1 (846 words)

	Formal Verification of a Snoop-Based Cache Coherence Protocol Using Symbolic Model Checking (Site not responding. Last check: 2007-11-05)
		Formal verification of cache coherence in a multiprocessor environment is essential in ascertaining the validity of a cache coherence protocol.
		Although a number of cache coherence verification techniques are available, very few authors have reported results on verification of cache coherence protocols using symbolic model checking.
		We have developed a set of modeling strategies that we found useful in verifying cache coherence of two to five processor configurations.
	doi.ieeecomputersociety.org /10.1109/ICVD.1999.745162 (274 words)

	Token based cache-coherence protocol (US6981097)
		A cache coherence mechanism for a shared memory computer architecture employs tokens to designate a particular node's rights with respect to writing or reading a block of shared memory.
		The token system provides a correctness substrate to which a number of performance protocols may be freely added.
		iii) allow a processor to read from at least a portion of the shared collection of data through its cache only if the processor has at least one of the tokens for that portion.
	www.delphion.com /details?pn=US06981097__ (272 words)

	W&B Scientific - Evaluation of Cache Coherence (Site not responding. Last check: 2007-11-05)
		Homepage -> Cache -> Evaluation of Cache Coherence
		Harris, B., and Tanenbaum, A. Auk: A methodology for the construction of cache coherence.
		A Methodology for the Synthesis of Write-Back Caches
	wbsci.org /Cache/1441/Evaluation-of-Cache-Coherence.html (1908 words)

	(via CobWeb/3.1 planetlab1.cs.virginia.edu) (Site not responding. Last check: 2007-11-05)
		Cooperative caching is a promising technique to avoid the increasingly formidable disk bottleneck problem in distributed storage systems; it reduces the number of disk accesses by servicing client cache misses from the caches of other clients.
		In this paper, we describe a new storage system architecture, split caching, and a new cache coherence protocol, fragment reconstruction, that combine cooperative caching with efficient support for fine-grained sharing and transactions.
		We also present the results of performance studies that show that our scheme introduces little overhead over the basic cooperative caching mechanism and provides better performance when there is fine-grained sharing.
	www.pmg.lcs.mit.edu.cob-web.org:8888 /pubs/adya97fragment-abstract.html (235 words)

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