
	Where results make sense

Topic: Cache miss

	Reducing Cache Miss Rate
		Capacity misses can occur for large matrices since it may not be possible to store all the elements of Z in the cache.
		The number of misses in the cache divided by the total number of memory accesses to this cache (Miss rateL2 for the 2nd-level cache).
		Since the L2 cache is large, the effect of increasing conflict misses (as is true for a smaller cache) is minimal.
	www.cs.umbc.edu /~plusquel/611/slides/chap5_3.html (1330 words)

	CPU cache - Wikipedia, the free encyclopedia
		A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory.
		A victim cache is a cache used to hold blocks evicted from a CPU cache due to a conflict or capacity miss.
		The victim cache lies between the main cache and its refill path, and only holds blocks that were evicted from that cache on a miss.
	en.wikipedia.org /wiki/CPU_cache (6673 words)

	Cache - Wikipedia, the free encyclopedia
		In computer science, a cache (pronounced kÄsh) is a collection of data duplicating original values stored elsewhere or computed earlier, where the original data are expensive (usually in terms of access time) to fetch or compute relative to reading the cache.
		Caches have proved extremely effective in many areas of computing, because access patterns in typical computer applications have locality of reference.
		The cache of disk sectors in main memory is usually managed by the operating system kernel or file system.
	en.wikipedia.org /wiki/Cache (1605 words)

	Patent 4370710: Cache memory organization utilizing miss information holding registers to prevent lockup from cache ...
		The cache memory consists of a set-associative cache section consisting of tag arrays and control with a cache buffer, a central memory interface block consisting of a memory requester and memory receiver together with miss information holding registers section consisting of a miss comparator and status collection device.
		Also, while the previously miss information block is in transit from memory, data from it may be requested by either the instruction or executing units and the status held in the miss information holding registers updated accordingly for output; the central memory is not accessed unless necessary.
		On a miss and previous miss hit where the cache buffer block was reallocated for the same input address before all the data was received, the miss information holding register is set obsolete in order to prevent possible subsequent multiple hits in the miss comparator 34.
	www.freepatentsonline.com /4370710.html (4914 words)

	cache - Definitions from Dictionary.com
		Caches rely on two properties of the access patterns of most programs: temporal locality - if something is accessed once, it is likely to be accessed again soon, and spatial locality - if one memory location is accessed then nearby memory locations are also likely to be accessed.
		In a write-through cache, data is written to main memory at the same time as it is cached.
		When the cache is full and it is desired to cache another line of data then a cache entry is selected to be written back to main memory or "flushed".
	dictionary.reference.com /browse/cache (997 words)

	Calculating the Cache Hit and Miss Rates
		So it is possible to have an 85% cache hit rate and a 1% cache miss rate, with the remaining 14% being accounted for by direct reads.
		This discussion of direct reads leads naturally to the observation that it is really the cache miss rate, rather than the cache hit rate, that should influence your sizing of the database buffer cache.
		Because cache hits are rare for serial long table scans, and impossible for direct reads, it is reasonable to assume that the cache miss rate can only be reduced by avoiding single block reads.
	www.ixora.com.au /tips/tuning/cache_miss.htm (883 words)

	Cache (Site not responding. Last check: 2007-10-17)
		Fully associative cache is equivalent to the special case of N-way set associative cache where N is chosen such that N equals the total number of blocks in the cache, i.e., such that there is only one index set.
		The miss penalty, or the time we are delayed when we have a cache miss, is increased since when we bring the data into the cache we must copy more data, which takes more time.
		A capacity miss occurs when a memory location is accessed once, but later because the cache fills up, that data is discarded, and then when we get a miss when accessing that memory location again because that data is no longer in memory.
	www.duke.edu /~twf/cps104/cache.html (7284 words)

	Data Cache Miss Rates (Site not responding. Last check: 2007-10-17)
		Associativity is varied with a different color of line; for example, a direct-mapped cache (associativity = 1) is represented by a green line, and a 16-way associative cache by a light blue line.
		Thus, each cache size on the graph has 5 lines associated with it (one for each associativity), and each line has 9 points associated with (one per block size).
		Since these are the traffic results, the y-axis shows the miss rate (in a percentage) that occured during the course of a simulation.
	www.cs.wisc.edu /~remzi/IRAM/p1.dcachemiss.html (173 words)

	[No title]
		cache pollution outside the cache - “stream buffers” on miss check stream buffer before memory access 1-block stream buffer reduces instr.
		set, let the compiler insert prefetches register prefetch cache prefetch nonfaulting or non-binding prefetches no-ops if address being prefetched would cause a fault what should the CPU be doing while the instr.
		in cache itself (almost like increasing the line size) => cache pollution outside the cache - “stream buffers” on miss check stream buffer before memory access 1-block stream buffer reduces instr.
	www.cc.gatech.edu /classes/cs6760_98_winter/slides/cache2.ppt (521 words)

	File Cache Miss Rate Chart (Site not responding. Last check: 2007-10-17)
		The File Cache Miss Rate chart displays the percentage of times that the file cache did not contain requested data.
		A file cache miss occurs when a read request is for a disk block that is not in the file cache.
		When a system is lightly loaded, the percentage of misses for data maps and pin reads is higher; thus, the overall file cache miss rate is higher.
	www.concord.com /help/files/reports/glance/server/filMiss.html (304 words)

	Amazon.com: "cache miss model": Key Phrase page (Site not responding. Last check: 2007-10-17)
		See all pages with references to "cache miss model".
		Then we will present a cache miss model which is used to estimate the number of conflict misses needed to drive the optimization process.
		5 Accuracy of the Cache Miss Prediction Model and Its Implications The cache miss model presented in Section 3.
	www.amazon.com /phrase/cache-miss-model (350 words)

	Cachegrind: a cache-miss profiler
		Inclusive L2 cache: the L2 cache replicates all the entries of the L1 cache.
		The cache configuration simulated (cache size, associativity and line size) is determined automagically using the CPUID instruction.
		Thus it measures not the number of times the data cache is accessed, but the number of times a data cache miss could occur.
	www.lrz-muenchen.de /services/software/programmierung/valgrind/html/cg_main.html (2761 words)

	Cache Miss Equations: A Compiler Framework for Analyzing and Tuning Memory Behavior - Ghosh, Martonosi, Malik ... (Site not responding. Last check: 2007-10-17)
		Cache Miss Equations: A Compiler Framework for Analyzing and Tuning Memory Behavior (1998)
		Cache miss equations: a compiler framework for analyzing and tuning memory behavior.
		Cache Miss Equations: An Analytical Representation of Cache..
	citeseer.ist.psu.edu /291244.html (810 words)

	Miss Rate
		The miss rate reduction achieved by HAC relative to the two page-caching systems is not very impressive for this particular traversal and cache size because T1 is a traversal with very good clustering (as discussed in Section 4.1.1), and the cache can fit only 55% of the objects accessed by the traversal.
		HAC is space-efficient: it needs only 11% more cache space than the bare minimum to run T1 without cache misses, and it needs only 1% more than the minimum if the number of secondary scan pointers is increased to 23.
		Since GOM partitions the client cache into object and page buffers statically, all data for GOM were obtained by manual tuning of the buffer sizes to achieve ``the best possible'' [KK94] performance; the sizes of the buffers were tuned for each cache size and for each traversal (e.g., tuning was different for T1 and T2b).
	www.pmg.lcs.mit.edu /papers/hac-sosp97/node19.html (1970 words)

	EFFICIENT CACHE MISS DETECTION TECHNIQUES FOR HIGH PERFORMANCE PROCESSORS (Site not responding. Last check: 2007-10-17)
		However the size of caches are limited since access times increase with cache size and aggressive processors perform multiple accesses to the caches in a single cycle.
		The MNM can be accessed in parallel with a level 1 cache access or after a level 1 cache miss.
		Naturally the MNM is most useful where is there is a considerable number of cache misses and these misses can be identified using small structures.
	www.research.ucla.edu /tech/ucla03-295.htm (419 words)

	Cache miss rate
		Most of the time is spent in the first two functions, so I wonder if I get a serious performance degradation with the cache misses for the two first functions and also with the level two cache misses of the =operator.
		A rough rule of thumb is a penalty of 10x for a level 1 cache miss and 200x for a level 2 cache miss.
		From your figures, just under a quarter of the total reading and writing time of your program is spent on cache misses in those three functions.
	www.codecomments.com /message155995.html (361 words)

	Cache Miss Equations: (ResearchIndex) (Site not responding. Last check: 2007-10-17)
		An Analytical Representation of Cache Misses Somnath Ghosh Margaret Martonosi...
		Effective transformations require detailed knowledge about the frequency and causes of cache misses in the code.
		5.6% : Cache Miss Equations: An Analytical Representation of Cache..
	citeseer.ist.psu.edu /586584.html (407 words)

	Data Dictionary Cache Miss Per Second Per Cache
		The Data Dictionary Cache is the part of the shared pool used to hold definitions of dictionary objects in memory.
		The Data Dictionary Cache Miss Per Second Per Cache chart shows cache-misses per second for each cache with the data dictionary.
		The chart will indicate whether or not an exorbitant amount of dictionary cache misses exists, and which sub-cache is experiencing the most misses.
	www.df.lth.se /~egh/doc/EM/Webhelp/dba/DBA_C18CHT59.HTML (221 words)

	Geneseo CSci 380 Cache Miss Penalty (Site not responding. Last check: 2007-10-17)
		Look at write buffer on a read miss, only stall for the writes if they would write the data you're going to read
		2 or more caches: small and fast near CPU, larger and slower between this and memory
		Little cache for blocks kicked out of main cache - can be recalled quickly
	www.cs.geneseo.edu /~baldwin/csci380/fall2003/misspenalty1103.html (154 words)

	[No title]
		Memory Address - 503 Cache Index - 119 Cache Tag - 3 *************************** Cache Miss**!
		Memory Address - 520 Cache Index - 8 Cache Tag - 4 *************************** Cache Miss**!
		Memory Address - 517 Cache Index - 5 Cache Tag - 4 *************************** Cache Miss**!
	www.cc.gatech.edu /classes/AY2002/cs2200_spring/hw/hw7/out3 (23685 words)

	[No title] (Site not responding. Last check: 2007-10-17)
		large cache misses After a cache miss interval, e.g.
		Only the predicted subarray is precharged before accessing cache.
		Prediction is verified after address is generatedóä¨Predictive Precharging Scheme¡ªóÉ÷¨+Bitline leakage power reducing architecture¨ùI-cache Subarray Prediction (ISP) unit Use Most Recently Used (MRU) scheme When a misprediction, Current cache access is aborted by ABORTi signal.
	www.cse.psu.edu /~cg539/sp04/lec11.ppt (461 words)

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