| | Digital chrominance signal processing system - Patent 4743961 (Site not responding. Last check: 2007-10-08) |
 | | The delayed chrominance signal is supplied to a chroma inverter 110 in which the phase of the subcarrier thereof is inverted and the resulting inverted chrominance signal C' is then combined with the luminance signal Y by an adder 106. |
 | | 3,564,123, comprises input and output transformers 111 and 112, with the chrominance signal C being supplied to a terminal 113 of the input transformer 111 and a chrominance signal C', the phase of which is inverted, as required, being developed at a terminal 114 of the output transformer 112. |
 | | Consequently, the chrominance signal applied to the input side of the output transformer 112 is made to have an opposite polarity to the preceding polarity so that when the command signal is at "H" level, the phase-inverted chrominance signal C' is developed at the output terminal 114. |
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