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Topic: Clock cycle

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	Clock signal - Wikipedia, the free encyclopedia
		A clock signal oscillates between a high and a low state, normally with a 50% duty cycle, and is usually a square wave.
		Such sine wave clocks are often differential signals, because this type of signal has twice the slew rate, and therefore half the timing uncertainty, of a single-ended signal with the same voltage range.
		The clock signal is usually distributed across a chip by a recursive H tree.
	en.wikipedia.org /wiki/Clock_cycle (552 words)

	Instructions Per Cycle - Wikipedia, the free encyclopedia
		In computer architecture, Instructions Per Clock (Instruction Per Cycle or IPC) is a term used to describe one aspect of a processor's performance: the average number of individual assembler instructions executed for each clock cycle.
		The number of instructions per second for a processor can be derived by multiplying the instructions per clock and the clock speed (measured in cycles per second or Hz) of the processor in question.
		The number of instructions executed per clock is not a constant for a given processor; it depends on how the particular software being run interacts with the processor, and indeed the entire machine, particularly the memory hierarchy.
	en.wikipedia.org /wiki/Instructions_Per_Clock (484 words)

	Clock Speed
		To compare this with a clock in the hall, lets say the high voltage signal is a "tick" and the low voltage signal is a "tock".
		If the mainboard clock is 100 MHz and the CPU "multiplier" is 24, then the internal clock cycles 24 times for every tick of the mainboard clock, producing a CPU speed of 2.4 GHz.
		DDR (double data rate) memory transfers data twice per cycle (on the tick and again on the tock) and is therefore often quoted as having a speed that is twice the actual clock speed (200, 266, 333, or 400 MHz).
	www.yale.edu /pclt/PCHW/clockidea.htm (2471 words)

	Novel connection found between biological clock and cancer
		The researchers found that the resetting effect of DNA damage requires the period-4 clock protein, and that period-4 is the homolog, the Neurospora version, of the mammalian checkpoint kinase.
		This closes a loop connecting the clock to period-4 and period-4 to the clock and the cell cycle.
		The clock normally modulates expression of this gene that encodes an important cell cycle regulator, and that cell cycle regulator in turn affects not only the cell cycle but also the clock.
	www.eurekalert.org /pub_releases/2006-06/dms-ncf062806.php (552 words)

	MusicWonk Clock Modules (Site not responding. Last check: 2007-10-31)
		Because Clock modules create time events, they should be at a higher priority than the modules that read their clock values.
		Putting a clock later in the priority chain than a module that uses it will cause the slaved module to be 1 clock tick behind the clock, which will result in an audible 1-tick glitch, regardless of synchronization.
		Because clock timings are in ticks, the accuracy of the On duration time is limited to the number of ticks in the duration.
	algoart.com /help/musicwonk/clocks.htm (5188 words)

	Researchers build diagram of cell cycle clock
		The cell cycle is one of life's most important processes, dictating cell division in virtually all aspects of life.
		Understanding the fundamental cycle of how a cell knows when to divide is key to finding out what goes wrong in diseases such as cancer, where cells divide uncontrollably.
		Simon found that a transcriptional activator from one stage of the cell cycle also activates transcriptional activators in the next stage of the cell cycle—creating a series of switches connected in a circular network.
	www.eurekalert.org /pub_releases/2001-09/wifb-rbd092801.php (778 words)

	ScienceMaster - JumpStart - Biological Clock
		Jet lag is an inconvenient reminder that the body is set to a 24-hour clock, known by scientists as circadian rhythms, from the Latin circa dies, "about one day." An internal biological clock is fundamental to all living organisms, influencing hormones that play a role in sleep and wakefulness, metabolic rate, and body temperature.
		Although biological clocks have been the focus of intensive research over the past four decades, only recently have the tools needed to examine the molecular basis of circadian rhythms become available.
		Researchers made the clocks glow by engineering transgenic strains of flies in which the same genes that illuminate a jellyfish and a firefly's tail are attached to PER.
	www.sciencemaster.com /jump/life/bio_clock.php (757 words)

	EDN Access--02.17.97 Circuit conditions variable-duty-cycle clock
		The input-clock signal serves as the clock signal to a D flip-flop, which is configured as a toggle flip-flop.
		The flip-flop's output signal is thus a 50%-duty-cycle, half-frequency version of the input clock, independent of the input-clock duty cycle.
		The output duty cycle is (t/T)·100%, where T is the period of the incoming (and now output) clock signal.
	www.edn.com /archives/1997/021797/04DI_01.htm (356 words)

	Glossary Search Results
		Computer clocks run voltage through a tiny crystal that oscillates at a predictable speed to give a meaningful timing method to the computer.
		One clock cycle doesn't necessarily mean that the processor does one operation.
		It is one way of gauging the performance of a microprocessor; however, different processor architectures dictate that a higher clock speed in one architecture does not always mean better performance over a lower clock speed in another architecture.
	www.geek.com /glossary/glossary_search.cgi?clock (255 words)

	Jitter Measurements for CLK Generators or Synthesizers - Maxim/Dallas
		Jitter is defined as "the short-term variation of a signal with respect to its ideal position in time." In a clock generator chip, there are many factors which contribute to output clock jitter, such as the device noise, supply variation, jitter in the reference clock, loading condition, and interference coupled from nearby circuitry.
		When the clock jitter is 10 times or larger than the triggering jitter of the oscilloscope, the clock jitter can be measured by triggering at a rising edge of the clock signal and measuring the jitter at the next rising edge.
		Because of the relation of power spectrums of the clock signal and the phase noise, shown in Figure 5, designers often use the compression (in dB) from the power of the tone to the envelope of the noise power spectrum at a certain frequency apart from fC to measure the quality of a clock signal.
	www.maxim-ic.com /appnotes.cfm?an_pk=2744 (1116 words)

	Interactive Fly, Drosophila
		Drosophila Clock (Clk) is rhythmically expressed, with peaks in mRNA and protein (Clk) abundance early in the morning.
		Clk mRNA cycling is regulated by Period-Timeless (Per-Tim)-mediated release of Clk- and Cycle (Cyc)-dependent repression.
		Within a Drosophila Clock intron, a second ORF is found with significant similarity to the mammalian gene EB1, implicated in binding the adenomatosis polyposis coli (APC) C terminus (Allada, 1998).
	www.sdbonline.org /fly/neural/clock1.htm (2257 words)

	Halfbakery: Sleep Cycle Alarm Clock (Site not responding. Last check: 2007-10-31)
		At the end of these cycles, we normally wake up and adjust our position before falling asleep again - often never remembering in the morning that we had woken at all.
		When it detects the end of a sleep cycle, it determines whether the current time is within the boundary - so in the example given, this would be any time from 07:00.
		If the clock reaches the time set without the alarm being triggered, it activates regardless of the stage in the sleep cycle.
	www.halfbakery.com /lr/idea/Sleep_20Cycle_20Alarm_20Clock (402 words)

	HHMI's BioInteractive - Is There a Clock in Your Head?
		Internal clocks keep pace with the 24-hour cycle of day and night and light and dark, enabling organisms to adapt their behavior accordingly.
		Researchers have concluded that sunrise can reset the clock but that the clock does not depend on sunrise and sunset to keep time.
		Understanding the detailed workings of the circadian clock may explain why heart attacks occur more often in the morning and why the incidence of asthma is more common at night, for example.
	www.hhmi.org /biointeractive/clocks/clocks_main.html (686 words)

	Interactive Fly, Drosophila
		The Clock gene plays an essential role in the manifestation of 24 h circadian rhythms in mice and is a member of the basic helix-loop-helix (bHLH) PER-ARNT-SIM (PAS) superfamily of transcription factors.
		Drosophila Clock protein induces transcription of the circadian rhythm genes period and timeless.
		Drosophila Clock protein (dClock) is a transcription factor that is required for the expression of the circadian clock genes period (per) and timeless (tim).
	www.sdbonline.org /fly/neural/clock3.htm (10647 words)

	Digital Clock Macro - Fall 2003
		The Zerowidth parameter defines the time in seconds that the clock will be at the zero state for each period of the clock cycle.
		The Onewidth parameter defines the time in seconds that the clock will be at the one state for each period of the clock cycle.
		The period of the clock cycle is the sum of the Zerowidth and Onewidth parameters.
	www.spectrum-soft.com /news/fall2003/dclock.shtm (576 words)

	The clock that wakes you when you are ready - mech-tech - 14 April 2005 - New Scientist
		The clock, called SleepSmart, measures your sleep cycle, and waits for you to be in your lightest phase of sleep before rousing you.
		The point in that cycle at which you wake can affect how you feel later, and may even have a greater impact than how long or little you have slept.
		You program the clock with the latest time at which you want to be wakened, and it then duly wakes you during the last light sleep phase before that.
	www.newscientist.com /article.ns?id=mg18624956.600 (429 words)

	[No title] (Site not responding. Last check: 2007-10-31)
		During // the 3rd and 4th calls the 1st sub-cycle output will be 1 and during // the 5th and 6th calls the 2nd sub-cycle output will be 1.
		Both the number of sub-cycles and the duration // of the sub-cycles can be defined when the Clock instance is declared.
		If the Advance parameter // of the Cycle function is false the call does not count as a call for // the SubCycleDelay of the current sub-cycle.
	www.dickinson.edu /~braught/courses/cs251s97/Clock.h (355 words)

	EDN Access -- 03.03.94 FPGA transfers data on every clock cycle (Site not responding. Last check: 2007-10-31)
		During write cycles, the timing between the write-enable signal, WE-, and the address bus, A[12:0], is critical.
		But, because the address changes on the same rising edge of the clock that turns off WE-, a race condition occurs and the address-hold time on the device's internal address bus (A[12:0]_I) is unpredictable.
		The low portion of the clock's cycle determines the basic cycle timing of WE-.
	www.edn.com /archives/1994/030394/05di4.htm (253 words)

	Dartmouth Medical School - Novel Connection Found Between Biological Clock and Cancer
		Dunlap is a co-author of the paper with DMS colleagues Dr. Jennifer Loros, professor of biochemistry, graduate student Christopher L. Baker, and former students Antonio M. Pregueiro and Qiuyun Liu.
		The researchers found that the resetting effect of DNA damage requires the period-4 clock protein, and that period-4 is the homolog--the Neurospora version-- of the mammalian checkpoint kinase.
		The coordination of the clock and cell division through cell cycle checkpoints, supports the clock's "integral role in basic cell biology," conclude the researchers.
	dms.dartmouth.edu /news/2006_h1/29jun2006_dunlop.shtml (614 words)

	CMSC 415, MSCS 521 Computer Architecture
		Assume that the datapath hasn't changed and that, as usual, the clock cycle is too short to allow an ALU operation and a register file access in a single clock cycle if one of them is dependent upon the other.
		M2: A machine like the multicycle datapath of Chapter 5, except the register updates are done in the same clock cycle as a memory read or ALU operation.
		M3: A machine like M2 except that effective address calculations are done in the same clock cycle as a memory access.
	www.academic.marist.edu /~jzbv/architecture/Homework/HW6MultiCycle2.htm (779 words)

	Cosmic Clock "Initiation Cycle" Cards
		"The Cosmic Clock predicts the soul's outpicturing of her psychology through the cycles of returning positive and negative karma.
		Mind the cycles of the hours, the days and the years.
		Mind the cycles of your astrology as you chart your stars on the Cosmic Clock.
	www.chelanews.com /cosmic.htm (272 words)

	Vertex/pixel shader instruction clock cycles - DevMaster.net Forums
		they have the throughput of 1 clock cycle, the latency can be really high, but it's quite easy to mask away with the really long pipelines.
		Latencies are also one clock cycle (for arithmethic instructions) as far as I know.
		Their clock frequency is low enough to perform things like a dot product in one clock cycle.
	www.devmaster.net /forums/showthread.php?p=33908#post33908 (1908 words)

	clock cycle - a Whatis.com definition
		In a computer, the clock cycle is the time between two adjacent pulses of the oscillator that sets the tempo of the computer processor.
		The clock speed is determined by a quartz-crystal circuit, similar to those used in radio communications equipment.
		For these reasons, there is no simple, universal relation among clock speed, "bus speed," and millions of instructions per second (MIPS).
	searchsmb.techtarget.com /gDefinition/0,294236,sid44_gci555039,00.html (228 words)

	Infoceptor Forums :: starcraft / warcraft / diablo - Clock cycle
		The one advantage of realism is somewhat lessened by the fact that friends and guild members from all over the world will play on a specific time-zone server, causing some members to forever play day at night or night during the day.
		With any clock cycle that is a divisor of 24, if you play at same time every day, you will always see the same time ingame.
		A clock only a few hours shorter would still take a realistically long time to shift from day to night, just like a 24-hour cycle.
	www.infoceptor.com /forums/showthread.php?t=14029 (2271 words)

	Clock Inside The Circadian Clock Discovered
		At night, two other genes (clock and cycle) stimulate production of Period and Timeless proteins, which begin to accumulate in the cell's cytoplasm.
		Prior studies, which examined the placement of Period and Timeless during different stages of the cycle, seemed to indicate that the two proteins idle in a cell's cytoplasm until they bump into each other and then, bound together, enter the nucleus.
		You have a clock within a clock." He notes that this precise timer shows how carefully orchestrated interactions between proteins really are.
	www.medicalnewstoday.com /medicalnews.php?newsid=36114 (795 words)

	Emulation system having multiple emulator clock cycles per emulated clock cycle (US5920712)
		An emulator system allowing a single cycle in a system clock in a user circuit to be emulated in multiple cycles of the emulator system clock.
		The emulator system provides a unique architecture permitting gates in the emulator to be used to emulate functions in the user circuit without requiring a fixed correspondence between a gate in the emulator and a gate in the user circuit.
		The emulator system operates in synchronous and asynchronous clock modes and allows the user system clock to be stopped during emulation in selected modes while still maintaining accurate emulation.
	www.delphion.com /details?pn10=US05920712 (745 words)

	Instructions per clock (John R. Mashey)
		b) Over time, clock rates would tend to improve for everybody at about the same rate, simply because people tended to get the newest process technology at about the same times, and clock rates were often driven by access times to affordable SRAMs for off-chip L1 caches.
		More often than not, one thinks of a cycle either as the time to do an ALU operation (specifically, an integer add), or maybe, a cache access.
		In general, the scalability of a design (which was what IPC was trying to get at, i.e., what would be achieved by better processes) is not determined by the number of gate delays in most paths, but by the number of gate delays in the slowest path, and it only takes one.
	yarchive.net /comp/instr_per_clock.html (946 words)

	The Evolving Memory Landscape (Site not responding. Last check: 2007-10-31)
		The actual memory core clock is 1/2 the clock rate "seen" by the system.
		DDR1, by contrast, clocks the core at the same speed as the external I/O clock.
		DDR1 CAS latencies could be as low as 2 clock cycles, though typical modules in OEM systems are 2.5 or 3 clocks.
	www.thechannelinsider.com /article2/0,1759,1633375,00.asp (732 words)

	Key Cycle Home (Site not responding. Last check: 2007-10-31)
		Learn how This Cycle of Keys can help you.
		This Clock shows the Cycle of Keys in such a way that allows you to understand and work with music like a professional.
		Ultimately, you will be composing, beautiful melodies and harmonies yourself, and feedback of your success in this field would be greatly appreciated.
	www.yellow.co.nz /site/keycycle (450 words)

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