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	Cross clock domain clocking for a system using two clock frequencies where one frequency is fractional multiple of the ...
		This invention relates to circuits and methods for transferring signals across clock domains and particularly to input and output cells for a processor having a core that operates at a frequency that is a half-integer multiple of a bus clock frequency.
		Bus signals are commonly synchronized with the rising edges of the bus clock signal, but when the processor clock frequency is a non-integer multiple of the bus clock frequency, the rising edge of the processor clock signal that is closest in time to a rising edge of the bus clock signal may be significantly offset.
		A higher-frequency clock signal clocks the latch, and a control circuit enables rising-edge or falling-edge latching depending on whether a rising edge or a falling edge of the higher-frequency clock signal is closest in time to a required edge of a lower-frequency clock signal.
	www.freepatentsonline.com /5915107.html (7494 words)

	Reference Clock Drivers
		The local clock driver also supports an external synchronization source such as a high resolution counter disciplined by a GPS receiver, for example.
		When more than one clock driver is supported, it is often the case that each shows small systematic offset differences relative to the rest.
		To reduce the effects of jitter when switching from one driver to the another, it is useful to calibrate the drivers to a common ensemble offset.
	www.ing-steen.se /share/text/school/ntp/refclock.htm (1089 words)

	Mercury Atomic Clock Keeps Time with Record Accuracy
		Better frequency standards can be used to improve probes of magnetic and gravitational fields for security and medical applications, and to measure whether “fundamental constants” used in scientific research might be varying over time—a question that has enormous implications for understanding the origins and ultimate fate of the universe.
		An optical atomic clock has three components: an atom that switches from one energy level to another when probed by a laser at a well-defined optical frequency; the laser used to induce this transition; and a counter that faithfully records each oscillation per unit time (the ticks) of the probe laser.
		The NIST mercury clock is unusual in part because of the method for stabilizing the ultraviolet laser used to probe the clock transition.
	www.nist.gov /public_affairs/releases/mercury_atomic_clock.htm (1128 words)

	DS3112 Clock Rates and Frequency Tolerances of the Transmit Clock - Maxim/Dallas
		On average, the internal clock is the same frequency as the external clock since the level in the FIFO is used to generate the internal clock, keeping the FIFO close to half full.
		The DS3112 samples the DS1(E1) input clocks using the DS3(E3) clock and detects the low to high transition that is used to enable the internal high-speed system clock for one clock period.
		The divisors to the DS1 clock are 29 and 28, the divisors for E1 are 17 and 16, and the divisors for G.747 are 22 and 21.
	www.maxim-ic.com /appnotes.cfm?an_pk=378 (1424 words)

	EEProductCenter.com :: Wide Range of Output Frequencies Differentiates Fully Integrated Clock (Site not responding. Last check: )
		C programmable clock source that gives designers the flexibility of using a single clock chip to generate clock frequencies from 21.25 to 1360 MHz.
		C frequency increment and decrement commands are most effective in frequency margin and system test environments.
		The MPC92432 clock synthesizer allows customers to perform much more functionality testing within the system, said John Fairholme, director of Freescale's Timing Solutions Operation in Chandler, Ariz. The synthesizer has various adjustable dividers and multipliers, which allows designers to apply a fixed-input clock frequency and generate almost any output frequency required by their system.
	www.eeproductcenter.com /analog/showArticle.jhtml?articleID=49400145 (1332 words)

	[No title] (Site not responding. Last check: )
		Increases in clock frequency for the P4 produce a proportionately greater increase in performance than increases in clock frequency for the P3.
		Intel claims that the P4 was designed to operate at higher clock frequencies and compares the P4 to the P3 at dissimilar clock frequencies.
		When a processor has been designed to run at a higher clock frequency the cost of increasing the clock frequency is low compared the the increased cost of a new micro architecture.
	www.cs.umd.edu /class/fall2001/cmsc411/proj01/p4/enhancement.html (414 words)

	Audio-DAC Performance Investigation - Maxim/Dallas
		The MAX9850 is an audio DAC that features unique clocking circuitry that allows it to achieve good audio performance from a wide range of master-clock frequencies.
		Clock frequencies that are compatible with integer mode are not commonly used by other parts of a system.
		Because this clock is already available in the system, it is simpler to use this clock for audio rather than a dedicated clock.
	www.maxim-ic.com /appnotes.cfm?an_pk=3735 (1208 words)

	EEProductCenter.com :: Programmable clock, the universal timing solution?
		Clock networks are traditionally designed using simple components such as fan-out buffers, clock generators, delay lines, zero delay buffers and frequency synthesizers.
		Five output clock frequencies can be generated, you can direct any frequency to any output in the output routing matrix, and the universal fan-out buffer drives up to 20 outputs organized in 10 banks with different voltages.
		The frequency of the PLL is the basis for generating the skew steps, which is a good reason for choosing the maximum PLL frequency of 640 MHz.
	www.eeproductcenter.com /analog/showArticle.jhtml?articleID=26800116 (1757 words)

	Stratix Clock Management Features (Site not responding. Last check: )
		Clock switchover is useful for video applications that require a manual switch between operation frequencies.
		The clock switchover capability is widely implemented in telecom, storage and server markets, as these markets require highly reliable clocking schemes to insure system reliability.
		Stratix frequency synthesis and programmable delay features can be changed by users on-the-fly; for example, designers can modify the PLL output frequencies and clock delays in prototype environments.
	www.altera.com /products/devices/stratix/features/stx-pll_features.html (741 words)

	Support FAQs (Site not responding. Last check: )
		Frequencies higher than 50MHz require the use of a TTL Clock Oscillator as the clock source.
		For frequencies higher than 50 MHz, it is recommended to use external clock oscillator devices.
		At the frequencies present, an unacceptable level of interference may be radiated and may result in unstable oscillation.
	www.parallax.com /sx/support_faqs2.asp (2646 words)

	The Microarchitecture of the Pentium® 4 Processor
		The final frequency of a specific processor pipeline on a given silicon process technology depends heavily on how deeply the processor is pipelined.
		The frequency of each section of logic is set to be appropriate for the performance it needs to achieve.
		The highest frequency section (fast clock) was set equal to the speed of the critical ALU-bypass execution loop that is used for most instructions in integer programs.
	www.intel.com /technology/itj/q12001/articles/art_2d.htm (727 words)

	Demos On Demand
		The output skew of each clock net relative to the reference input can be controlled further in delay increments of 156 ps (lead or lag) to compensate for differences in circuit board clock network trace length.
		Clock Network Layout is Simplified by Compensating for Timing Delays Due to Clock Trace Length Differences - Traditionally, clock network designs are constrained to maintain equal clock trace lengths to ensure timing integrity using serpentine patterns to accommodate the extra length clock traces.
		However, the increased jitter in the clock is frequently not desirable.
	www.demosondemand.com /dod/press/?press_id=1570 (919 words)

	Factors to Consider When Clocking the TNT4882 at Frequencies Less Than 40 MHz- Developer Zone - National Instruments
		Clocking at lower frequencies has little effect besides slowing down some internal functions.
		If the clock frequency of the TNT4882 is lower than 40 MHz, you can set the T1 delay to wait for fewer CLOCK cycles.
		The pulse width of the TRIG signal is one CLOCK period.
	zone.ni.com /devzone/cda/tut/p/id/3339 (971 words)

	EETimes.com - System view of core clock frequency, voltage (Site not responding. Last check: )
		FV adjustment is based on semiconductor physics dictating that core voltage can be reduced if core clock frequency is reduced and that the power consumed by a microprocessor core is roughly proportional to the clock frequency at which it runs and the square of the voltage at which it is powered.
		But since power equals energy divided by time and because software tasks may take longer to complete at lower clock frequencies, the total energy consumed at lower clock frequencies is not guaranteed to be appreciably different than at higher frequencies.
		In this case, increasing the clock frequency has a negligible impact on performance-the data can't arrive any faster, no matter what the core clock frequency-so the idle time stays at 0 percent.
	www.eetimes.com /news/latest/showArticle.jhtml?articleID=51201329 (1347 words)

	Fujitsu Introduces New Spread Spectrum Clock Generator (SSCG) Devices Developed to Reduce EMI at High Frequencies : ...
		The MB88151 has a built-in frequency multiplier and is capable of providing an output frequency of 8.3 MHz up to 133.4 MHz, with modulation rates of ±0.5 percent and ±1.5 percent for center spread and -1.0 percent and -3.0 percent for down spread.
		The MB88152 and MB88153, each of which features a power-down pin and external clock input, provide input and output frequencies of 20 MHz to 134 MHz, with modulation rates of +/-0.5 percent or +/-1.5 percent for the center spread, and -1.0 percent or -3.0 percent for the down spread.
		The MB88154 provides a reference clock output, and input and output frequencies of 20 MHz to 67 MHz, with modulation rates of +/-0.5 percent, +/-1.0 percent or +/-1.5 percent for the center spread, and -1.0 percent, -2.0 percent or -3.0 percent for the down spread.
	www.fujitsu.com /us/news/pr/fma_20040308-04.html (536 words)

	Bitsum Technologies Wiki - WRT54G (Site not responding. Last check: )
		The base frequency used for the BCM3302 0.8 is determined by the crystal in use on the PCB, and is 12.5mhz.
		Oddly, clock frequencies don't seem to necessarily have to be divisible by this base, e.g.
		The developers of OpenWrt and DD-WRT swear to me that the clock frequency is set only by the CFE, and not also by the linux kernel driver for the BCM processor.
	www.bitsum.com /openwiking/owbase/ow.asp?WRT54G (1870 words)

	Technological Innovation Management Enterprises, Inc. TIMEUSA.com (Site not responding. Last check: )
		The CG-1 Clock Generator and Frequency Counter is a hand held test instrument which provides six crystal based clock outputs and measures input frequencies from 1Khz through 10Mhz.
		The clock outputs and the external frequency counter input (when in Counter Mode) frequencies are displayed on the integral 4-digit LED display.
		The output clock frequency is selected through a push button switch located on the front panel which sequences through the available six frequencies (+/-4ppm) and the Counter Mode.
	www.timeusa.com /clock.htm (271 words)

	EETimes.com - Techniques to make clock switching glitch free
		With more and more multi-frequency clocks being used in today's chips, especially in the communications field, it is often necessary to switch the source of a clock line while the chip is running.
		The two clock frequencies could be totally unrelated to each other or they may be multiples of each other.
		A glitch on the clock line is hazardous to the whole system, as it could be interpreted as a capture clock edge by some registers while missed by others.
	www.eetimes.com /news/design/showArticle.jhtml?articleID=16501239 (1440 words)

	3.3Vdriver - CDC9841 - TI Product Folder (Obsolete) (Site not responding. Last check: )
		The CDC9841 is a high-performance clock synthesizer/driver that generates all required clock signals necessary for a high-performance PC motherboard.
		The six peripheral-component-interconnect (PCI) clock outputs (BCLKn) are half the frequency of PCLKn and are delayed 1 ns to 4 ns from the rising edge of the CPU clock.
		The PCI and 12-MHz clock frequencies are derived from the base CPU and 24-MHz clock frequencies, respectively.
	focus.ti.com /docs/prod/folders/print/cdc9841.html (496 words)

	XFree86: e:/XFree86 for RH 8.0/XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/ati/aticlock.c Source File
		ATI says there is no reliable way for the driver to determine 00051 * which clock generator is on the adapter, but this driver will do its best to 00052 * do so anyway.
		Video memory corruption and other 00779 * effects occur because, at this early stage, the clock probe 00780 * cannot reliably be prevented from enabling frequencies that are 00781 * greater than what the adapter can handle.
		Clocks" 01090 " will be reordered.\n"); 01091 break; 01092 } 01093 } 01094 } 01095 } 01096 else 01097 /* Ensure crystals are not matched to clock chips, and vice versa */ 01098 01099 #ifndef AVOID_CPIO 01100 01101 if ((pATI->Chip <= ATI_CHIP_18800)
	www.cs.mtu.edu /~cjblazek/d8/d0/aticlock_8c-source.html (1929 words)

	PreSonus DigiMAX FS \| Sweetwater.com
		The DigiMAX FS is loaded with new patented JetPLL jitter reduction technology ensuring ultra-high converter performance, fast and robust locking through a wide range and variation of frequencies and noise shaping to remove nearly all audio band jitter.
		It's extremely robust and tolerant of wide variations in clock frequencies.
		It has built in word clock, and the pres absolutely BLOW AWAY the 002 rack preamps.
	www.sweetwater.com /store/detail/DigiMaxFS (658 words)

	Stereophile: The Jitter Game
		Rather than ask readers to calculate the clock period from the oversampling rate and figure out the relative jitter levels for themselves, we have decided to normalize all jitter measurements to the very common 8x-oversampling clock found in virtually all current multi-bit CD players and D/A converters.
		Note that the ratio between the jitter deviation and the clock frequency is identical for 3ps of jitter on a 384x clock and 144ps on an 8x-oversampling clock.
		By multiplying 5.89ps by 48 (the ratio between a 384x clock and an 8x clock), we get 283ps, slightly lower than the 371ps measured at the 8x clock (the higher jitter at the 8x clock is probably a result of dividing the master 16.9MHz clock to obtain the 352.8kHz clock).
	www.stereophile.com /reference/193jitter/index7.html (898 words)

	Cypress Semiconductor Introduces Clock chip
		Designers can use the new InstaClock programmable clock generator kit to program InstaClock samples with any configuration in a set of defined frequencies in less than a minute, eliminating the lead time of waiting for custom-programmed parts or for a mask change.
		Another benefit is that the kit reduces the number of components necessary for multiple frequencies by providing the same footprint for a wide range of configurations and applications.
		By allowing for self-serve programming, the kit enables engineers to streamline the process of tuning clocks and to reduce the development cycle as clock requirements and board designs change during prototype development.
	rfdesign.com /vlf_to_uhf/cypress_semiconductor_frequencies (434 words)

	FreeVGA - VGA Display Generation
		The dot clock source in the VGA hardware is selected using the Clock Select field.
		The Dot Clock Rate field specifies whether to use the dot clock source directly or to divide it in half before using it as the actual dot clock rate.
		The 9 dot clock mode was included for monochrome emulation and 9-dot wide character modes, and can be used to provide 360 and 720 pixel wide modes that work on all standard VGA monitors, when combined with a 28 Mhz dot clock.
	www.osdever.net /FreeVGA/vga/vgacrtc.htm (1769 words)

	LAUTERBACH - TRACE32 FIRE Fully Integrated RISC Emulator
		Since high speed RISC processors operate at bus frequencies of more than 100 MHz, a redefinition of the traditional emulator hardware was necessary.
		The result of this new concept TRACE32-FIRE was developed especially for applications with RISC Processors, Integrated Controllers and DSPs at highest clock frequencies, without loosing the capabilities of a traditional In-Circuit Emulator.
		clock speed at a voltage range from 2.7 to 5.5V.
	www.lauterbach.com /fire.html (536 words)

	Lucid Genx6-96 Word Super Clock Generator (Site not responding. Last check: )
		Dedicated word clock devices have been on the professional recording scene for some time now.
		Many people agree that a stable clock can dramatically improve the fidelity and recording quality of everything from individual component parts to the most well known digital audio workstations (DAW).
		The GENx6-96 is capable of generating 4 clock frequencies: 44.1, 48, 88.2, and 96kHz.
	www.rmcaudio.com /LUCID/genx6_96.htm (427 words)

	Cypress solutions allow programming of popular frequencies
		Cypress Semiconductor Corp. has introduced a clock chip and self-service programming kit that together promise to enable programming of commonly used frequencies.
		Designers can use the new InstaClock Programmable Clock Generator kit to program InstaClock samples with any configuration in a set of defined frequencies in less than a minute, Cypress said, eliminating the lead-time of waiting for custom-programmed parts or for a mask change.
		The CY36800 programming kit provides access to the most commonly used clock frequencies with a simple software selection and supplies a standard part number that can be ordered from authorized distributors.
	www.eetasia.com /ART_8800426677_499485_30f4bcec200607_no.HTM (354 words)

	Tight Timings vs High Clock Frequencies \| Tom's Hardware
		The theoretical 290 MHz measurement with tight timings could be both lower and higher, depending on how much of a bottleneck the CPU clock frequency turned out to be, as also noted earlier.
		At higher CPU clock frequencies, the importance of memory speed is larger both in SuperPI and in 3DMark01.
		In SuperPI, the gain from tight timings (at 203 MHz memory clock) was 3.2% at 2030 MHz CPU clock, and 5.1% at 2610 MHz.
	www.tomshardware.com /2006/03/31/tight_timings_vs_high_clock_frequencies/page9.html (473 words)

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