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Topic: Clock rate

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	Does a clock's acceleration affect its timing rate?
		In other words, the accelerated clock's rate is identical to the clock rate in a "momentarily comoving inertial frame" (MCIF), which we can imagine is holding an inertial clock that for a brief moment slows to a stop alongside the accelerated clock, so that their relative velocity is momentarily zero.
		The clock postulate is not meant to be obvious, and it can't be proved.
		The clock postulate is one of the ideas we use to build the theory of gravity known as general relativity.
	math.ucr.edu /home/baez/physics/Relativity/SR/clock.html (2548 words)

	Clock rate - Wikipedia, the free encyclopedia
		The clock rate is the fundamental rate in cycles per second, measured in hertz, at which a computer performs its most basic operations such as adding two numbers or transferring a value from one processor register to another.
		Usually when referring to a computer, the term "clock rate" is used to refer to the speed of the CPU.
		The clock rate of a CPU is normally determined by the frequency of an oscillator crystal.
	en.wikipedia.org /wiki/Clock_rate (558 words)

	Clock signal - Wikipedia, the free encyclopedia
		A clock signal oscillates between a high and a low state, normally with a 50% duty cycle, and is usually a square wave.
		A clock signal might also be gated, that is, combined with a controlling signal that enables or disables the clock signal for a certain part of a circuit.
		Such sine wave clocks are often differential signals, because this type of signal has twice the slew rate, and therefore half the timing uncertainty, of a single-ended signal with the same voltage range.
	en.wikipedia.org /wiki/Clock_signal (553 words)

	Determination of Ginga Clock Rate
		The average clock period is always within a few microseconds of 8 s, and provides a basis for assigning time of observation to the data by linear interpolation between successive clock comparisons.
		In order to investigate the stability of the clock rate, the clock period was computed for a segment of data approximately 20 days in duration, from 1988 August 23 to 1988 September 3.
		We suspected that a major portion of the variation in clock rate was due to temperature variations in the clock circuit, and so we next investigated temperature variations in the satellite.
	ledas-www.star.le.ac.uk /ginga/temperature/clock_rate.html (248 words)

	[No title] (Site not responding. Last check: )
		In the preferred embodiment, the beat clock rate is (32/31) x the chip rate and the 4x chip rate is used as the second input of the clock source switch 348, although other clock rates may be used.
		The clock signal 361a is used to advance or delay the beginning of the local sequence 362 in fractional intervals of the clock rate, which in the preferred embodiment is 8x the chip rate.
		This rate is derived from the master clock using a divide-by-9 function and is the reduced sampling rate at which the local PN sequence 362 is sampled and correlated with the received PN sequence once alignment between the received and local sequences is established.
	www.wipo.int /cgi-pct/guest/getbykey5?KEY=00/03507.000120&ELEMENT_SET=DECL (4772 words)

	[No title] (Site not responding. Last check: )
		Preferably the frequencies at each of the desired rates at which data is sampled at the last stage of the decimator is an integer multiple of the so-called 1x rate for each of the standard signals to be converted by its respective channel.
		clock rate; Figure 4 is a graph showing the output from the low pass filter at 8x-WCDMA rate; and Figure 5 is a graph showing the output of the MRADC after resampling the signal at 2x-GSM clock rate.
		The over-sampling ratio between both clock rates is related to the amount of noise aliased in the signal band by the re-sampling operation due to the harmonics of the re-sampling square wave signal.
	www.wipo.int /cgi-pct/guest/getbykey5?KEY=03/30372.030410&ELEMENT_SET=DECL (3521 words)

	THE BELL SYSTEM
		The history of precision clock development consists largely of the choice and design of stable resonant elements and of devising means for using them so that as far as possible their inherent properties alone control their rates of oscillation.
		It is necessary to apply a correction for the rate of the Shortt clock, and the ultimate accuracy with which the absolute value of frequency is known depends on the accuracy of the time signals which are used to determine the rate of the clock.
		Since the rate of a crystal clock is the rate of oscillation of the crystal or of the current driving it, it is only necessary, in comparing clock rates, to measure the relative frequencies of the oscillators concerned.
	www.ieee-uffc.org /freqcontrol/marrison/Marrison.html (17535 words)

	Embedded.com - FPGA Clock Schemes
		The maximum clock rate is determined by the propagation time, P, of a signal between two flip-flops in the design.
		However, since the received data rate is independent of the board we are designing (and we cannot assume we are getting data from a source that uses the same clock for all of the E2 muxes), the E2 demux clocks must be allowed to operate at slightly different rates.
		Be advised that the advertised rate is the best-case scenario rate.
	www.embedded.com /showArticle.jhtml;jsessionid=4MP5KROIEOIL0QSNDBCSKHY?articleID=9901007 (3602 words)

	Phoenix OSFS: Phx::Clock Class Reference
		Most Clock types will define what their reference time is, and this will generally determine the rest of the Clock's behavior.
		A pointer to a new Clock::Task attached to this Clock.
		As this Clock changes (either by the client changing it or by its internal clock advancing), the Timer will change by a corresponding amount, adjusted for the rate of the timer.
	www.stanford.edu /~acoates/ppdoc/html/class_phx_1_1_clock.html (444 words)

	CPU (Central Processing Unit) - PC Hardware Help
		The "clock rate" is usually used to reference the speed of the CPU.
		The frequency of an oscillator crystal is used to determine the clock rate.
		Clock rates can be misleading and should not be used to compare the performance of processors from different families or manufacturers.
	www.pchardwarehelp.com /CPU.php (721 words)

	Implementation
		A real-time clock is a hardware device that pulses regularly an integral number of times each second, and interrupts the CPU each time a pulse occurs.
		In Xinu, the clock rate of the real-time clock is 60Hz.
		Thus the clock rate of 60 Hz is divided by 6 to 10 Hz.
	www.cs.unc.edu /~dewan/242/s02/notes/int/node4.html (970 words)

	EETimes.com - FPGA Clock Schemes
		The maximum clock rate is determined by the propagation time, P, of a signal between two flip-flops in the design.
		However, since the received data rate is independent of the board we are designing (and we cannot assume we are getting data from a source that uses the same clock for all of the E2 muxes), the E2 demux clocks must be allowed to operate at slightly different rates.
		Be advised that the advertised rate is the best-case scenario rate.
	www.eetimes.com /story/OEG20030210S0053 (3474 words)

	DPLL Clock Recovery
		The transmit clock is taken directly from the BRG at the data rate specified in ClockSpeed.
		The clocks are generated by dividing the oscillator frequency by a divisor which allows only specific data rates to be generated exactly.
		A DPLL application that requires a data rate than cannot be exactly generated may still work if the difference between the exact rate and the actual rate is small enough and if a sufficient number of transitions on RxD are maintained.
	www.microgate.com /techcenter/htmlhelp/html/hdlc937d.htm (666 words)

	How is the Convert (Channel) Clock Rate Determined in NI-DAQmx and Traditional NI-DAQ? - KnowledgeBase - Support - ...
		Note:The Convert (Channel) Clock rate is the inverse of interchannel delay, for example a Convert (Channel) Clock rate of 80,000 Hz corresponds to an interchannel delay of 12.5 µs.
		At slower scan rates 10 µs of delay is added to the fastest possible channel conversion rate of the board (the same as the maximum scan rate) to derive the Channel Clock.
		As the scan rate increases, there comes a point where there is not enough time for a full 10 µs of additional delay time between channel conversions and still finish acquiring all channels before the next edge of the Scan Clock.
	digital.ni.com /public.nsf/allkb/42484E84DA98053686256D32006E0494 (761 words)

	ANSDIT - The letter "C" (Site not responding. Last check: )
		A clock is generally used for regulating the time of state transitions, synchronizing multiple events, or measuring time intervals inside the electronic device.
		The pulse rate of the output of the clock.
		The clock rate is given in hertz (Hz), kilohertz (kHz), megahertz (MHz), or gigahertz (GHz).
	www.ncits.org /tc_home/k5htm/c2.htm (1941 words)

	Clock Recovery and Rehab
		If you trigger a sampling scope with this type of recovered clock, because jitter is causing the trigger and data to move by the same amount and in the same direction, the acquired signal will be very clean.
		Ideally, the clock should be a perfect sinusoid, but the module is designed to cope with distorted clocks more often seen in practice.
		If the reference clock sampler is ignored for the moment, this mode mimics that of a traditional sampling scope except that the actual data sampling is performed by the 82A04.
	www.evaluationengineering.com /archive/articles/0407/0407clock_recovery.asp (3023 words)

	VMware Knowledge Base - Answer (Site not responding. Last check: )
		When a guest asks for more than 1000 clock interrupts per second, it can be difficult for the virtual machine to keep up, especially if other applications are running on the host at the same time.
		Even on real hardware, clock interrupts are sometimes lost because the operating system is busy for more than 1 millsecond and another clock interrupt comes in before the previous one was handled.
		One approach to a slow guest clock is to reduce the guest timer interrupt rate.
	www.vmware.com /support/kb/enduser/std_adp.php?p_faqid=1420 (1187 words)

	Dictionary of Computers - clock rate
		Every computer contains an electronic clock, which produces a sequence of regular electrical pulses used by the control unit to synchronize the components of the computer and regulate the fetch–execute cycle by which program instructions are processed.
		Clock rates are measured in megahertz (MHz), or millions of pulses a second.
		The tassel is a symbol of the monarchy.
	www.tiscali.co.uk /reference/dictionaries/computers/data/m0034449.html (246 words)

	The Eureka Clock
		In this graph, the rate can be seen to change on the order of two minutes a day, over and over, throughout the 40 minute sample period.
		It's possible that the choppiness of the rate could be reduced with careful cleaning, and I have not yet investigated this.
		It is often not possible to bring a clock to rate with the usual adjustments.
	www.bmumford.com /clocks/eureka/eureka.html (740 words)

	FPGA Clock Schemes
		The propagation time is the sum of the hold time required for the signal to change at the output of th e first flip-flop, plus the delay of any combinatorial logic between stages, plus the routing delay between stages, plus the set-up time for the signal going into the flip-flop at the second stage.
		We have not yet eliminated any clocks, but th e E2 clocks are now based on the E3 clock.
		Even though the output of the first flip-flop can be used as long as all of the paths out go to flip-flops clocked by the same clock, it is generally good practice to use a circuit such a s that in Figure 6 to isolate metastability to one short line.
	www.us.design-reuse.com /articles/article4854.html (3413 words)

	Elysian Audio: Halcyon DAC - Asynchronous Sample Rate Converter (Site not responding. Last check: )
		The input to the DAR is from an externals source and the quality of the decoded clock will not be perfect and may even have missing samples.
		By doing this the internal DAC clock is isolated completely from the input clock unless under gross uncorrectable catastrophic data/timing errors.
		A side effect of course is to convert the input at its arbitrary sample rate and word length to the desired output.
	www-personal.engin.umich.edu /~jglettle/section/halcyon/asrc.html (391 words)

	HI-TECH Software Forums: i2c clock rate
		i'm a bit confused as to what the i2c clock rate is? i've successfully implemented i2c, but only by example.
		Hi Andre, the best way to check the real clock rate is to put an ocilloscope at the SCL pin and let the software transfer some bytes.
		Uwe >i'm a bit confused as to what the i2c clock rate is? > >i've successfully implemented i2c, but only by example.
	www.htsoft.com /forum/all/showflat.php?Number=5128&page= (142 words)

	baudline solution - sample rate stability
		It is important to check the relationship between the input and output sample rates when operating in the full duplex mode.
		The 48000 to 44100 sample rate conversion is a difficult ratio for polyphase filter generation but this is an unrelated problem since it doesn't explain why the ADC and the DAC clocks would need to be different.
		It is meant to be an indicator of the average sample rate since the start of the test and not the true instantaneous sample rate.
	www.baudline.com /solutions/sample_rate/index.html (2600 words)

	What is clock speed? - A Word Definition From the Webopedia Computer Dictionary
		Every computer contains an internal clock that regulates the rate at which instructions are executed and synchronizes all the various computer components.
		Ideally, the CPU clock speed and the bus clock speed should be the same so that neither component slows down the other.
		In practice, the bus clock speed is often slower than the CPU clock speed, which creates a bottleneck.
	www.webopedia.com /TERM/C/clock_speed.html (300 words)

	Clock Rate Command Enhancements Feature Module
		The following example shows how to configure serial interface 5/0 with a clock rate that is rounded to the nearest value that is supported by the hardware.
		To configure the clock rate for the hardware connections on serial interfaces such as network interface modules (NIMs) and interface processors to an acceptable bit rate, use the clock rate interface configuration command.
		In this example, the clock rate is adjusted to 1151526 bps.
	www.cisco.com /univercd/cc/td/doc/product/software/ios111/ca111/clkrate.htm (657 words)

	Changing the Top-Level FPGA Target Clock Rate (FPGA Module) - LabVIEW FPGA Module 8.2 Help
		If you select a clock rate that is too fast for the FPGA VI, the Compilation Failure dialog box tells you the compile failed.
		A derived clock is a clock you create from a base clock that you can use as a clock for an FPGA Module application.
		The top-level clock is the global clock that the FPGA VI uses outside a single-cycle Timed Loop.
	zone.ni.com /reference/en-XX/help/371599B-01/lvfpgaconcepts/changingfpgaclkrate (394 words)

	Beyond3D - Which was nice. (Site not responding. Last check: )
		The core clock rate on the 7800 GTX is only an extra 30MHz over the 6800 Ultra, or 7.5% greater.
		With the higher clock speed and two extra vertex shaders the geometry rate of the 7800 GTX is 43% greater than the 6800 Ultra - again, we are looking for improvements beyond this in order to see how effective the changes to the vertex shader and fixed function elements of the geometry pipeline have been.
		Whilst 6800 has a 1:1 texture to ROP ratio, 7800 has a higher texture rate than it does ROP output, so with single texturing the performance gap between them is not much better than the clock rate differences.
	www.beyond3d.com /previews/nvidia/g70/index.php?p=07 (510 words)

	Temperature dependence of the Ginga clock rate
		The period of the clock aboard Ginga varies by one part in 10
		This temperature dependence makes it difficult to assign times of observation to the data with millisecond accuracy, particularly during remote orbits during which it is not possible to compare the onboard clock with a reference clock at the Kagoshima ground station.
		In this paper we investigate the relationship between satellite temperature and clock period, and show how this relationship can be used to estimate the clock period from the temperature data even when direct clock comparisons are not available.
	ledas-www.star.le.ac.uk /ginga/temperature/contents.html (160 words)

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