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Topic: Clock signal

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  Clock - Wikipedia, the free encyclopedia
Clocks are in homes and offices; smaller ones (watches) are carried; larger ones are in public places, e.g.
A clock is a recurrent, periodic process and a counter.
A clock face is the part of an analog clock that tells time through the use of a fixed numbered dial or dials and moving hand or hands.
en.wikipedia.org /wiki/Clock   (1424 words)

 Clock signal - Wikipedia, the free encyclopedia
A clock signal oscillates between a high and a low state, normally with a 50% duty cycle, and is usually a square wave.
The circuits using the clock signal for synchronization may become active at either the rising or falling edge, or both (see for example DDR SDRAM), of the clock signal.
Such sine wave clocks are often differential signals, because this type of signal has twice the slew rate, and therefore half the timing uncertainty, of a single-ended signal with the same voltage range.
en.wikipedia.org /wiki/Clock_signal   (302 words)

 Apparatus providing a clock signal for a digital television receiver in response to a channel change - Patent 5175626
Signal energy to assist in developing the clock signal can be added to the television signal in the form of a pilot signal, but the energy associated with such an added signal may degrade the television signal by introducing interference and unwanted artifacts.
The magnitude of the output signal from a nonlinear signal generator (e.g., multiplier) such as unit 131 in response to an input QAM signal is a function of the shape of the amplitude versus frequency characteristic of the input signal, particularly at the band edges.
Signal CC causes control network 155 to provide an output switching control signal S with a magnitude for causing switch 134 to occupy position B instead of position A. In position B the phase error control signal from the output of filter 138 is switched from synthesizer 129 to phase shifter 133.
www.freepatentsonline.com /5175626.html   (5075 words)

 Circuit for reproducing a clock signal - Patent 4390801
A circuit for reproducing a clock signal recited in claim 1 wherein the oscillation device comprises a resonant circuit that produces a damped oscillation caused by the input pulse and a square wave converter circuit that converts the output of the said resonant circuit to rectangular waves.
A circuit for reproducing a clock signal recited in claim 4 wherein the oscillation device comprises a resonant circuit that outputs a damped oscillation caused by the input pulse and a square wave converter circuit that converts the output of the said resonant circuit to rectangular waves.
Consequently, the phase of the signal in the interpolated period is determined, and a clock signal is accurately reproduced by the PLL circuit.
www.freepatentsonline.com /4390801.html   (4888 words)

 Glitchless clock signal control circuit for a duplicated system - Patent 4635249
These signals inhibited the buffers that serve the clock source that is being removed from an on-line status and they now enable the buffers that serve the clock signal source that is being switched from on-line to off-line.
The port board clock signal thus encounters no glitches or unwanted additional square waves during the switching between the two clocks since it is low the entire interval during which the control of its generation switches from the former to the new on-line clock source.
The off-line clock is operated as a slave of the on-line clock and the output of the off-line clock is synchronized from the on-line clock.
www.freepatentsonline.com /4635249.html   (12121 words)

 Clock signal   (Site not responding. Last check: 2007-11-06)
In synchronous digital electronics such as most computers a clock signal is a signal used to coordinate the actions of or more circuits.
A clock signal will oscillate between a high and a low normally with a 50% duty cycle.
The circuits using the clock signal synchronization may become active at either the or falling edge of the clock signal.
www.freeglossary.com /Clock_signal   (412 words)

 Device for transmitting a clock signal accompanied by a synchronization signal - Patent 4694291
The transmitter comprises a clock, a synchronization circuit connected to a selector circuit and a flip-flop the output of which is looped back to an input through the intermediary of a delay circuit and the selector circuit.
Such transmission devices are routinely used for controlling electronic devices from a single clock, and the synchronization signal generally corresponds to the elimination of one pulse of the clock signal which is achieved on transmission by the momentary modification of the clock signal frequency, requiring the clock signal to be reconstituted at the receiving end.
The signal HR, which is the complement of the signal HMR, comprises 25 ns clock pulses and 75 ns synchronization pulses; the signal HRO at the output of the delay line 41 is the signal HR delayed by 60 ns.
www.freepatentsonline.com /4694291.html   (903 words)

 INTERCONNECTION FORMATS   (Site not responding. Last check: 2007-11-06)
A clocking signal is generated by one device and sent to the other, allowing the devices to clock together.
The signal connection is used to transmit the clock and the data simultaneously.
This signal may be generated by one of the devices (DAW or main tape machine, for instance), or it may come from a dedicated clock generator, a device whose sole purpose is to create and establish a steady, reliable clocking signal that is then sent to each device.
www.mtsu.edu /~djbrown/connect.html   (1530 words)

 United States Patent Application: 0040090275
Then, a processing clock signal for use in a reproduction processing in the amplifier is set to a phase locked state based on the reference clock signal.
The phase locked state means a state in which a phase of the reference clock signal accurately agrees with a phase of the processing clock signal.
In the embodiment, the present invention is applied to the system in which it is detected whether or not a processing clock signal used as the reference of processing such as amplification processing in the amplifier is in a phase locked state.
appft1.uspto.gov /netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=/netahtml/PTO/srchnum.html&r=1&f=G&l=50&s1="20040090275".PGNR.&OS=DN/20040090275&RS=DN/20040090275   (5775 words)

 Clock signal   (Site not responding. Last check: 2007-11-06)
In synchronous digital electronics, such as most computers, a clock signal is a signal used tocoordinate the actions of two or more circuits.
The circuits using the clock signal for synchronization may become active at either the risingor falling edge of the clock signal.
The speed of a clock signal in a computer is called the clock rate.
www.therfcc.org /clock-signal-47641.html   (151 words)

 Clock signal distribution device (US4868522)
A delay circit is described which automatically adjusts the propagation delay of clock signals, generated by a clock source, distributed to various receiving devices so that the receiving devices are clocked simultaneously.
In one embodiment, the clock signal generated by a single clock source is independently delayed for each receiving device.
To determine the proper amount of delay, a clock signal is simultaneously transmitted to each of the receiving devices and a clock return signal from each receiving device is returned to a delay circuit via a return path.
www.delphion.com /details?pn=US04868522__   (258 words)

 Effects of Digital Crosstalk in Data Converters
Part 2: Crosstalk on the Clock - Maxim/Dallas
During this transition period, the clock signal is analog.
Noise on a data converter clock affects the point in time that the sample of the analog signal of a data converter (i.e., ADC input) is taken.
A pure sine wave at a frequency of 4, and the same sine wave with PM modulation at a frequency of 2 (which is equivalent to crosstalk onto the clock at a frequency of 2).
www.maxim-ic.com /appnotes.cfm/appnote_number/1841   (1059 words)

 Atomic Clock Synchronization using the WWVB time signal from Colorado
In operation, the clocks are based upon the characteristics of the Cesium 133 atom, whose single electron is known to vibrate at a standard 9,162,613,770 times a second.
The 60,000 Hz signal is always transmitted, but every second it is significantly reduced in power for a period of 0.2, 0.5 or 0.8 seconds: • 0.2 seconds of reduced power means a binary zero • 0.5 seconds of reduced power is a binary one.
The controlling radio signal for the National Physical Laboratory's clock is transmitted on the MSF 60kHz signal via the transmitter at Rugby, operated by British Telecom International.
www.ntp-time-server.com /atomic-clock/atomic-clock.htm   (1132 words)

 Effects of Digital Crosstalk in Data Converters
Part 3: Digital Data Signal Crosstalk on the Clock - Maxim/Dallas
When this clock samples the subsequent analog signal, the analog signal will be effectively phase modulated at the rate of the same signal.
In Part 1 of this article series, we mentioned that the effect of clocking jitter is directly proportional to the slope of the analog signal with respect to time.
The reason is while the picoseconds of jitter on the clock is typically independent of the frequency of the clock, the sidebands that show up on the clock measured with a spectrum analyzer will be higher with a higher frequency clock with the same amount of picosecond jitter, which makes them easier to see.
www.maxim-ic.com /appnotes.cfm/appnote_number/1842   (1373 words)

 EDN Access--02.17.97 Circuit conditions variable-duty-cycle clock
The input-clock signal serves as the clock signal to a D flip-flop, which is configured as a toggle flip-flop.
The flip-flop's output signal is thus a 50%-duty-cycle, half-frequency version of the input clock, independent of the input-clock duty cycle.
The addition of a flip-flop (a) to a clock doubler (b) turns the doubler into a clock generator that produces any desired output duty cycle.
www.edn.com /archives/1997/021797/04DI_01.htm   (356 words)

 NAT4882 CLOCK Signal Considerations - Tutorial - Development Library - National Instruments   (Site not responding. Last check: 2007-11-06)
The rising and falling edges of the CLOCK signal must be monotonic.
The minimum pulse width of the CLOCK signal high or low (Tpw in Figure 1) is 15 ns.
The pulse width of the TRIG signal is one CLOCK period.
zone.ni.com /devzone/conceptd.nsf/webmain/4B9CCFB9564B7DC9862568040063DB39?opendocument   (879 words)

 Clock signal - Encyclopedia.WorldSearch   (Site not responding. Last check: 2007-11-06)
A clock signal oscillates between a high and a low state, normally with a 50% duty cycle.
In other words, the signal is a square wave.
Signal seeking, digital display, clock radio/tape with electronic tuner (SAE)
encyclopedia.worldsearch.com /clock_pulse.htm   (239 words)

 The Extremist DAC
A digital signal is defined as a signal whose meaning comes from its state (0 or 1) at a particular time (say, when it is latched in a circuit).
Digital signals are very noise-proof because it takes a lot of noise to fake a digital level (change a 1 into a 0 for instance).
In this sense, it is an analog signal, as the timing information is defined by comparing the analog value of the clock signal with a fixed threshold and marking a clock tick every time the value crosses the threshold.
peufeu.free.fr /audio/extremist_dac/spdif.html   (1442 words)

 The Official Forum - Mechanics questions   (Site not responding. Last check: 2007-11-06)
The game clock timer is instructed and hour before every game by the appropriate official on just what signals are used to start and stop the clock are.
If you wind the clock when the ball is downed near the sideline in the first quarter, then you must do the same with less than a minute to go in the half or game.
Years ago the start the clock signal was not an approved NFHS signal for indicating the ball was in-bounds.
www.officialforum.com /printthread.php?threadid=2800   (1959 words)

 pn clock signal generator   (Site not responding. Last check: 2007-11-06)
Clock and signal inputs of fast ADCs usually are equipped with true...
The TXOUT signal is generated synchronizing with the CLOCK rising edge.
To generate this clock signal, called T-Clk, the sample clock on each device is...
www.bestgeneratorsguide.com /28/pn-clock-signal-generator.html   (376 words)

A phase correcting means (8) creates and transmits, by means of a number of auxiliary clock signals phase shifted with respect to each other and originating from an incoming clock signal (CKin), a recovered clock signal (CKut) for the data signal.
The recovered clock signal is fed to the phase detector (2), which detects a phase position error, if any, between the data signal and its recovered clock signal and emits information regarding this to the phase correcting means (8).
The invention allows shifting of the phase of a clock signal continuously an arbitrary number of turns forwards or backwards without interruptions or discontinuities in the recovered clock signal.
www.delphion.com /details?&pn=EP00619052B1   (289 words)

 Digital circuit for generating a clock signal #5539786   (Site not responding. Last check: 2007-11-06)
The ten megahertz clock signal then clocks the toggle Flip-Flop causing the Flip-Flop to change state.
At state S9 the state machine again provides an enable signal to the toggle Flip-Flop enabling the toggle Flip-Flop which allows the ten megahertz clock signal to change the state of the output of the toggle Flip-Flop.
This results in one megahertz clock signal at the output of the toggle Flip-Flop which is synchronized to the incoming serial data stream.
www.zyn.com /flcfw/fwpat/nvpm5539786.htm   (208 words)

 Voyager - Frequently Asked Questions
There is a sphere of radio transmission about thirty light years thick expanding outward at the speed of light, announcing to every star it envelops that the earth is full of people.
The "clock" is really a counter, based on one of several electronically generated frequencies.
The picture is made from this signal, which traces the picture as a series of vertical lines, similar to ordinary television (in which the picture is a series of horizontal lines).
voyager.jpl.nasa.gov /faq.html   (4093 words)

 Serial Links   (Site not responding. Last check: 2007-11-06)
Synchronous links use some form of clocking, by which a clock signal is transmitted along with the data.
The receiver latches the data signal on the trailing edge of the clock.
In this example, every zero bit is encoded as a full clock cycle, while one bits are encoded by skipping a transition in the middle of the cycle.
www.freesoft.org /CIE/Topics/64.htm   (535 words)

 기지국 / 무선 인프라 - Parts List
Spread-spectrum frequency synthesizer is designed to generate multiple clocks for clock distribution in network routers or switches
Clock generator provides multiple clock outputs and is ideal for network routers
Clock generator Is optimized for XDSL CO line cards and telecom systems requiring low-jitter clock outputs
korea.maxim-ic.com /solutions/base_stations/parts.mvp/scpk/1448/pl_pk/0   (127 words)

 EOPC - Optical Modulator and Chopper Locked to an External Clock Signal
The phase relationship to the clock is factory set to customer's requirements (0° to 360°), and is front panel adjustable in a range of ±45° minimum.
The chopper is phase locked to the clock signal
The chopper is self oscillating at its resonant frequency (the chopper is not locked to the clock)
www.eopc.com /sys_pld1c_extern.html   (283 words)

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