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Topic: Clock skew

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	Tips on Controlling Clock Skew
		This generic problem is often referred to as the "clock skew" problem.
		In a multi-level clock tree, we need to control the worst case skew between any of the leaf nodes, even if those leaf nodes are sourced by different driver chips.
		Some clock drivers use PLL technology to actually advance their output timing to the point where it closely matches the input timing, thus guaranteeing good input-to-output skew performance.
	www.sigcon.com /Pubs/straight/clockskew.htm (1094 words)

	Clock skew - Wikipedia, the free encyclopedia
		In circuit design, clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times.
		The second is distance: if the signal has to travel the entire length of a circuit, it will likely (depending on the circuit's size) arrive at different parts of the circuit at different times.
		On a network such as the internet, clock skew describes the difference in time shown by the clocks at the different nodes on the network.
	en.wikipedia.org /wiki/Clock_skew (182 words)

	CommsDesign - On-time Finish Rests With Multiple Clocks
		Clock control logic may be designed to pulse various clocks in a specific sequence or to ensure that certain clocks are not pulsed at the same time.
		To minimize skew during shift, all scan chains should be ordered such that all flops clocked by one clock domain are grouped together.
		If multiple clock domains are combined into one test clock, then careful attention also must be paid to the clock tree design to ensure that there will be no clock skew problems during the capture cycle.
	www.commsdesign.com /showArticle.jhtml?articleID=16504411 (2197 words)

	MAPLUG FAQ - Actel Clock Tree
		There is one global clock for the 1020 devices, 2 global clocks for the 1280’s, 3 global clocks for the 1460/14100’s (two routed, 1 dedicated), and up to 6 clocks (two global, 4 quadrant) in some models of the A3200DX family.
		Routing clock signals inside of an FPGA is not the same as routing a clock on a printed circuit board (PCB).
		This can result in the parallel clocking problem where hold times may not be met since the data to the flip-flop may change prior to the clock signal reaching the logic thresholds.
	klabs.org /richcontent/maplug/MAPLUG_Content/FAQ_Folder/ActelClockTree.htm (755 words)

	Clock Reference - Support
		It is a test board consisting of clock generator and buffer 4 of the buffered signal go to the DIMM socket while other clock signal go to a reference net.
		Clock delay and skew can be measured at the SDRAM chips on the module and then compared against the signal at the reference net.
		Clock skew is measured by comparison of the waveform at the “clock reference net” and the clock signal at the clock pin of the SDRAM.
	www.simmtester.com /page/products/clock/clksupp.asp (1654 words)

	Clock Skew [Rights Management Services] (Site not responding. Last check: 2007-11-05)
		Clock skew is when the clock time on one computer is a little different from the clock time on another computer.
		Clock skew can cause problems whenever you specify a validity time in a license.
		For example, if a publishing computer's clock is 15 minutes behind a consuming computer's clock, and the publisher creates an issuance license that expires in 15 minutes, the consumer would never be able to use this issuance license.
	msdn.microsoft.com /library/en-us/rms_sdk/rm/clock_skew.asp (370 words)

	TechOnLine - Predictability Counts When Designing Clock Signals
		Clock design is tightly coupled with various core components of a chip: library design, floorplanning, scan insertion, timing verification, and critical path networks.
		The clock's function is to synchronize all the latches and flip-flops, and to synchronize the data I/O with the internal operation.
		Clock skew can introduce new issues into the equation—for example, if skew is too large, a hold time violation can occur.
	www.techonline.com /community/ed_resource/feature_article/20416 (1351 words)

	TechOnLine - Phase- and Delay-Locked Loop Clock Control in Digital Systems
		The basic idea of the active closed-loop clock skew compensation is to reduce exactly as much clock skew as needed.
		To achieve clock division, it is sufficient to place a divider in the incoming clock path; in other words, PLLs are not necessary to perform divisions.
		When the clock edge of the second clock arrives, the second flip-flop shortly outputs the logic one, and both flip-flops are reset.
	www.techonline.com /community/related_content/14627 (2034 words)

	Clock Skew: Problem Overview and Actel Solutions (Site not responding. Last check: 2007-11-05)
		Clock skew is the difference in path delays from a clock input to each of the clock's loads.
		Clock skew can easily be measured by running a timing report in Actel's Designer and taking a quick look at the INPAD to CLOCK measurements This portion of the report measures the delay from input buffers to clock pins.
		If your clock skew is longer than the first entry in the list, you need to work on reducing or eliminating it.
	www.actel.com /apps/guru/dec99/hw1679.html (1058 words)

	EETimes.com - Clock Management with PLLs and DLLs
		Clock skew is the result of minor variations in the time at which clock signals arrive at their destinations, usually register clock pins.
		Clock skew occurs because the clock must be distributed throughout the system using board traces, connectors, backplanes, and chip-level input-clock driver pads and on-chip interconnect.
		Clock skew depends completely on the phase delay of the clock distribution network and the data-path delay such that hold time requirements aren't violated.
	www.eetimes.com /isd/cover_story/OEG20010328S0051 (2213 words)

	[No title]
		Clock Skew with Latches Assume all latches (1-4) are on the same clock and that the logic blocks are static.
		Assume that the clock skew between subsequent latches is the same (i.e.
		the skew from L1 to L2 is the same as the skew from L2 to L3).
	bwrc.eecs.berkeley.edu /Classes/ic541ca/ic541ca_s04/Homeworks/ic541ca_sp04_hw8.doc (570 words)

	Thread
		This is because at an operating frequency of 1 GHz, the available clock period is 1ns, and clock skew and jitter resulting in ±100ps uncertainty leads to a loss of 20% of the clock period due to this uncertainty.
		The definition of clock skew in itself appears to be very different between standard ASIC design (gate-based) and custom chip design such as high-performance CPUs that employ hand-crafted logic, manual placement and top-level design.
		Clock jitter estimation is an essential task in determining clock uncertainty.
	www.vsi.org /vsiConf/Thread.cfm?CFID=972817&CFTOKEN=11277196&&Thread_ID=11&mc=1 (743 words)

	Overhead of Clock Drift
		As we described in Section 3.3, SSCH tries to synchronize slot begin and end times, though it is also designed to be robust to clock skew.
		These practical values of clock skew are extremely small to impact the performance of SSCH.
		The drop in throughput is more for larger clock skews, although the throughput is still acceptable at 10.5 Mbps when the skew value is an extremely high 1 ms.
	www.cs.cornell.edu /people/ranveer/multinet/ssch/Overhead_Clock_Drift.html (264 words)

	Windows Time Server: Appendix H
		While f for a particular clock is a random variable with respect to the population of all clocks, for any one clock it ordinarily changes only slowly with time and can usually be assumed a constant for that clock.
		The clock-filter algorithm determines the selected clock offset theta (peer.offset), together with the associated roundtrip delay delta (peer.delay) and filter dispersion epsilon sub sigma, which is added to the associated sample dispersion epsilon sub i to form the peer dispersion epsilon (peer.dispersion).
		When a number of clocks are involved, it is not clear beforehand which are correct and which are not; however, as cited previously, there are a number of techniques based on clustering and filtering principles which yield a high probability of detecting and discarding incorrect clocks.
	www.bytefusion.com /windows-time-server/xp-2000-time-server/ntp-windows-time-server/appendixh.htm (3025 words)

	EDN Access--03.14.97 Growing your own IC clock tree
		The factors that contribute to clock skew include loading mismatch at the clocked elements, mismatch in RC delay due to clock-line segment-width and -length variations, and process variations induced during chip fabrication.
		Toshiba typically achieves a clock skew of less than 100 psec when using CTS on chips with maximum clock frequencies of 100 to 125 MHz.
		Clock trees often have wide traces at their roots and may also have long segments, making the trees more susceptible to inductance problems than are other chip nets.
	www.edn.com /archives/1997/031497/06CS.htm (2461 words)

	Clock Network Optimization
		As input it takes in a SPICE netlist of the clock network with interconnect and fanout load, latency requirements for the clock propagation, and generates a new netlist with resized drivers so that a zero-skew network is generated.
		Most clock skew synthesis tools employ drivers from a fixed set of cells with symmetric layout techniques to equalize interconnect lengths, grids, and dummy buffers to balance loads and reduce skew.
		Skew is a very non-linear function of the device sizes, balancing it over several hundred terminations is not an easy task.
	www.libtech.com /node31.html (788 words)

	[No title] (Site not responding. Last check: 2007-11-05)
		One prior art"fix"to the skew problem was to include a feedback clock and a single register to correct/control skew between data and the system clock.
		101 is also coupled to: clock input terminal 299 of first reset flip-flop 242; clock input terminal 240 of second reset flip-flop 244; clock input terminal 265 of read pointer flip-flop 261; clock input terminal 253 of write pointer enable flip-flop 251 and clock input terminal 285 of data-in flip-flop 281.
		According to one embodiment of the invention, the second clock signal rdclk is supplied by the same PLL that provides the signal lgclk.
	www.wipo.int /cgi-pct/guest/getbykey5?KEY=04/109523.041216&ELEMENT_SET=DECL (5019 words)

	CGS74CT2524 - 1 to 4 Minimum Skew (300 ps) Clock Driver [Obsolete] (Site not responding. Last check: 2007-11-05)
		These minimum skew clock drivers are designed for Clock Generation and Support (CGS) applications operating at high frequencies.
		Skew parameters are also provided as a means to measure duty cycle requirements as those found in high speed clocking systems.
		The CGS74CT2524 is a minimum skew clock driver with one input driving four outputs, specifically designed for signal generation and clock distribution applications.
	www.national.com /pf/CG/CGS74CT2524.html (194 words)

	Clock-skew Retiming (Site not responding. Last check: 2007-11-05)
		This technique allows late arriving signals to be sampled at a later point in time by intentionally introducing a skew on the clock input of the sampling register.
		Unused global clock lines in FPGAs can be used to distribute a finite set of clock skews to the entire circuit.
		This result is evocative as it may suggest future FPGA architectures that contain greater numbers of global clock lines, as we tradeoff gains in speed for greater power requirements from increased clock network flexibility.
	www.eecg.toronto.edu /~brown/papers/fpga02-singh.html (339 words)

	Celestry : Welcome : etc : etc (Site not responding. Last check: 2007-11-05)
		Striving to eliminate clock skew, they are unaware that perfect zero-skew is not the solution for either the safest or the highest performance design.
		However, purposely skewing clock arrivals to produce useful skew can achieve timing closure, increase design robustness, improve performance and even reduce simultaneous switching noise -- all by fixing just one signal.
		The true goal of clock design is to meet the timing requirements of the chip.
	www.celestry.com /products_clockwise.shtml (345 words)

	FPGA Clock Schemes
		If P is greater than the clock period, T, then when the signal changes at one flip-flop, it doesn't change at the next stage of logic until two clock cycles later.
		The skew, S, is the maximum delay from the clock input of one flip-flop to the clock input of another flip-flop.
		If the clock is not too fast to meet normal timing constraints, it is probably not going to propagate metastable states in a circuit such as Figure 6.
	www.us.design-reuse.com /articles/article4854.html (3398 words)

	Using Computer Clock Skew to Crack Anonymity Networks - security - ITinfo
		Clock skew, the tendency for a computer's clock to become less precise when heated, can reduce the efficacy of anonymizers, such as the Electronic Frontier Foundation's Tor network....
		Clock skew has long been a concern of engineers of synchronous network, as it causes the clock signal for system components to arrive at different times; however, Murdoch is the first to take advantage of this hardware fallibility.
		To understand how clock skew can be used to affect the security of anonymity networks, such as Tor, I think that we must first understand how Tor works.
	itrain.org /itinfo/using_computer_clock_skew_to_crack_anonymity_networks.php (541 words)

	Light Blue Touchpaper » Hot or Not: Revealing Hidden Services by their Clock Skew
		Absolute clock skew has been previously used to tell whether two apparently different machines are in fact running on the same hardware.
		My paper adds that because the skew depends on temperature, in principle, a PC can be located by finding out when the day starts and how long it is, or just observing that the pattern is the same as a computer in a known location.
		The clock skew is measured by requesting TCP timestamps, which is a feature enabled by all modern operating systems and seldom blocked by firewalls.
	www.lightbluetouchpaper.org /2006/09/04/hot-or-not-revealing-hidden-services-by-their-clock-skew (5575 words)

	» Track Any Computer on the Internet Using its Clock Skew Fingerprint (Site not responding. Last check: 2007-11-05)
		Clock skew is what a computer thinks the time is as compared to other time-keeping...
		The clock skew fingerprint is based on the work of University of California graduate student Tadayoshi Kohno, who explains that clock skew fingerprinting works by taking advantage of the fact that typically “each party in a TCP flow includes information about its perception of time in each outgoing packet.
		Says Kohno of his clock skew fingerprints “our technique can be mountable by adversaries thousands of miles and multiple hops away.” And without the clock skew fingerprintee’s knowledge that they and their computer are being tracked.
	www.theinternetpatrol.com /track-any-computer-on-the-internet-using-its-clock-skew-fingerprint (1515 words)

	clock skew
		In circuit design In circuit design, clock skew is a phenomenon in synchronous circuits in which the clock signal arrives at different components at different times.
		Due to the large die sizes and tight relative clock skew margins, the impact of interconnect manufacturing variations on the clock skew in today s...
		The skew is the overlap between the clocks.
	www.clock-guide.net /clock-skew (741 words)

	Xilinx : Clock Management
		In designs requiring multiple high frequency clocks, reduction of the number of high frequency clocks on the PCB can be achieved with clock management circuitry.
		The clock can also be phase shifted during configuration or phase stepped during operation, all with a resolution of 256 steps per clock period.
		Source-synchronous systems using clock forwarding have a narrow data capture window, in which the clock can be phase adjusted to capture data in the middle of the arriving eye pattern.
	www.xilinx.com /products/design_resources/highspeed_design/hsd_clockmanagement.htm (499 words)

	Re: DULUG: 5 hour clock skew (Site not responding. Last check: 2007-11-05)
		something uses this to compensate for the fact that no clock chip is perfect.
		perhaps this skew file is badly corrupt and instead of having info on the order of 3 s/day, maybe it has 5 hr/hr.
		I did nothing to change the clock, timezones, anything > before the problem first appeared.
	www.duke.edu /web/dulug/list/1016.html (237 words)

	Gtk-Gnutella: clock.c File Reference
		Maintain an accurate clock skew of our host's clock with respect to the absolute time.
		The routine clock_loc2gmt() is used to compute the real time based on the local time, given the currently determined skew.
		The skewing of the local time is only used when the host is not running NTP.
	gtk-gnutella.sourceforge.net /doxygen/clock_8c.html (489 words)

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