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 | | Due to different designers working independently, a number of timing, clocking, and testing issues were thrown over the wall to be taken care of, later, by the package designer. |
 | | The timing edges to the instruction decoder chip, datapath chips, and the cache controllers are supplied by the clock deskew chip [Nah94] as shown in Figure 4.10. |
 | | The layout environment, including the wire length and crossovers, between the clock receivers and the four phase generators on the chips are kept same for minimizing on-chip skew. |
| www.ecse.rpi.edu /frisc/theses/GargThesis/chapter4.html (4157 words) |
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