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| | Circuits and methods for characterizing the speed performance of multi-input combinatorial logic - US Patent 6850123 (Site not responding. Last check: 2007-10-21) |
 | | One or more multi-input combinatorial logic circuits is inserted into the loop so the oscillator produces a periodic signal having a period based, in part, on the delay through the combinatorial logic components. |
 | | Each flip-flop includes a data terminal D connected to a logic one (e.g., VDD), a clock terminal, a synchronous output terminal Q, and an asynchronous clear terminal C. Test circuits 210A and 210B, identical circuits in the depicted embodiment, are two-input combinatorial logic circuits. |
 | | To configure the flip-flops to respond to falling edges, the D inputs are connected to a logic voltage level representative of a logic zero and the clock terminals are inverted (i.e., are negative-edge triggered). |
| www.patentstorm.us /patents/6850123.html (4151 words) |
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