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| | Galaxy Design Platform |
 | | The concurrent optimization engines spend this savings to minimize power consumption, reduce area, lower test costs or increase yield. |
 | | Synopsys’ IC Compiler tool is a next-generation place-and-route system that provides all the functionality necessary for high-quality physical design including floorplanning, physical synthesis, placement, routing, timing, signal integrity (SI) optimization, power reduction, design-for-test (DFT), and yield optimization. |
 | | The unified CCS model for timing, noise and power, extends the analysis and optimization capabilities within the Galaxy Design Platform to concurrently address nanometer effects and thereby reduce design margins and minimizing iterations. |
| www.synopsys.com /products/solutions/galaxy_platform.html (864 words) |
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