| | United States Patent: 6,680,518 (Site not responding. Last check: 2007-10-19) |
 | | In another embodiment, a complementary metal oxide semiconductor (CMOS), inductance-enhancing integrated circuit includes a field effect transistor supported over a silicon-containing substrate and having a gate, a source, and a drain. |
 | | The CMOS inductance-enhancing circuit of claim 11, wherein the gate is configured to sample the output of the first inductor and the source is configured to drive the second inductor thereby increasing the effective inductance of the first inductor. |
 | | The conductors in these instances are still encased in oxide but are far removed from the silicon substrate by virtue of a large number of insulator and metal levels. |
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