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Topic: Conditional branch

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	Branch predictor - Wikipedia, the free encyclopedia
		In computer architecture, a branch predictor is the part of a processor that determines whether a conditional branch in the instruction flow of a program is likely to be taken or not.
		Branch predictors are crucial in today's modern, superscalar processors for achieving high performance.
		Branches evaluated as not taken decrement the state towards strongly not taken, and branches evaluated as taken increment the state towards strongly taken.
	en.wikipedia.org /wiki/Branch_prediction (2210 words)

	Encyclopedia: Conditional branch
		Conditional branches are often issued in speculative execution, primarily because there is no simple solution to predict which branch will be selected when the condition is evaluated.
		Branches where the results of the conditional statement affect the outcome of the branch's execution are particularly difficult because they cannot be executed speculatively at all in a strict programming language (C, C++, Java, BASIC, FORTRAN, and others) without substantial effort on the part of the programmer to allow for it.
		Since these languages form the bulk of existing commercial applications, the efficient use and executive optimization of branches is an important concern for many programmers working on applications, compilers, and CPU architectures.
	www.nationmaster.com /encyclopedia/Conditional-branch (290 words)

	[No title] (Site not responding. Last check: 2007-10-10)
		This form of branch prediction performance acceleration (the capability of predicting the outcome of a conditional branch instruction, and performing instruction prefetching from the resultant predicted instruction stream) is known as"branch address prediction." Other processors do not employ branch prediction techniques.
		Conditional branch instructions may test for a specific value or result of the condition evaluating instruction, or in some cases may contain the condition to be tested as part of the conditional branch instruction itself.
		When a branch instruction is being executed, CONDITION 218 is used in determining the results of the branch condition evaluation, and thus whether a branch is taken or falls through to the next sequential instruction.
	www.wipo.int /cgi-pct/guest/getbykey5?KEY=01/97021.011220&ELEMENT_SET=DECL (4682 words)

	Microprogram controller in which instruction following conditional branch instruction is selectively converted to a NOP ...
		When the branch condition is satisfied, the target address of branch ADR is loaded to the program counter and at the same time, the instruction of the (n+2)th address is executed as shown in FIG.
		In the branch microinstruction, MC15="0", MC14="0" and this represents that the microinstruction is the branch microinstruction.
		In the case of a nonconditional branch microinstruction, for example, the output of the battery 16, that is, the high level output, is unconditionally applied to one of the input terminals of the NAND gate 17.
	www.freepatentsonline.com /4773002.html (3723 words)

	[No title]
		This is the branch processing unit (BPU), an execution unit which acts as the rudder that steers the front end (and behind it the rest of the processor) through the instruction stream.
		Static branch prediction is simple, and relies on the assumption that the majority of backwards pointing branches occur in the context of repetitive loops, where a branch instruction is used to determine whether or not to repeat the loop again.
		The Branch Target Buffer (BTB) stores the branch targets of previously executed branches, so when a branch is taken the BPU grabs the speculative branch target from the BTB and points the front end to begin fetching instructions from that address.
	arstechnica.com /articles/paedia/cpu/p4andg4e.ars/4 (1460 words)

	C:\BELLBOOK\P001-100\HTMFILES\CSP0297.HTM
		The discontinuity is minimized, when the branch is not taken, through special handling of the condition code (CC) and the conditional branch instruction (BC).
		The condition code is a two-bit indicator, set according to the outcome of a variety of instructions, and can subsequently be interrogated for branching through the BC instruction.
		The organization assumes that, for a conditional branch, the CC will not be valid when the "branch-on-condition" (BC) is decoded (a most likely situation, considering that most arithmetic and logical operations set the code).
	research.microsoft.com /users/gbell/Computer_Structures_Principles_and_Examples/csp0297.htm (607 words)

	Program Control Instructions
		Often, a conditional branch instruction will be immediately preceeded by a compare instruction, whose purpose is to compare two operands (without altering either) and set the flags accordingly.
		However, a conditional branch can also be used after most data movement and arithmetic instructions, because these set the condition codes on the basis of comparing the result of the operation to zero.
		Many of the conditional branch instructions come in two versions, depending on whether the last operation is to be interpreted as working on unsigned numbers or a signed numbers.
	www.cs.gordon.edu /courses/cs222/lectures/program_control.html (2627 words)

	C:\BELLBOOK\P001-100\HTMFILES\CSP0302.HTM
		A conditional branch instruction, because it is data dependent and therefore less predictable in its outcome than other branch instructions, requires special consideration in setting up loop mode.
		In retrospect, the conditional philosophy and its effects on loop mode, although significant to the performance of the CPU and conceptually simple, were found to require numerous interlocks throughout the CPU.
		The complications of conditional mode, coupled with the fact that it is primarily aimed at circumventing storage access delays, indicate that a careful re-examination of its usefulness will be called for as the access time decreases.
	research.microsoft.com /~gbell/Computer_Structures_Principles_and_Examples/csp0302.htm (778 words)

	REPORT
		Conditional branches are major obstacles to achieve higher performance for a high performance CPU.
		Branches impede machine performance in that conditional branch is not resolved until the condition is resolved and the target address is calculated, and unconditional branch is not resolved until the target address is calculated.
		Branch behavior of a program is a very important factor, if not the most important, to determine the performance of any branch prediction schemes.
	www.cs.ucdavis.edu /~su/Berkeley/cs252/project.html (7072 words)

	Program Control Instructions
		Both conditional branches are I format instructions, and look like this # of bits 6 5 5 16 field name op rs rt immediate value contents op = first second offset 4 for beq reg to reg to (two's complement 5 for bne compare compare signed number) 3.
		Both conditional branches specify the destination of the branch as an offset relative to the value currently in the PC.
		It is conceivable that a problem could arise with the initial conditional branch at the start of a very large switch statement.
	www.cs.gordon.edu /courses/cs311/lectures-2003/branches.html (1551 words)

	Citations: Interprocedural Conditional Branch Elimination - Bodik, Gupta, Soffa (ResearchIndex)
		The simplest form of branch elimination is loop unrolling, in which instances of backedge branches are removed by replicating the body of the loop.
		In the second category of control flow optimization, branch reordering, the order in which branches are evaluated is changed to reduce the average depth traversed through a network of branches [22] The final category of control flow optimization research focuses on the reduction of control....
		Finally, conditional branches have been coalesced together into an indirect jump from a jump table [6] This method extends the use of an indirect jump table far beyond the translation of a multiway statement and allows many other 8 coalescing opportunities to be exploited.
	citeseer.ist.psu.edu /context/125550/11728 (2877 words)

	Conditional Branches, Interlacing the Paths After (Site not responding. Last check: 2007-10-10)
		By interlacing the paths after a conditional branch like test, both paths are provided to the cpu with a simple double wide instruction fetch mechanism.
		Interlaced execution continues until 1.a branch in the executing path is executed or 2.a branch is detected in the not executing path, after which sequential instruction fetch resumes (because the not executing path has ended).
		With regard to conventional conditional branches, it takes time to lookahead in the instruction stream, identify a conditional branch instruction, calculate the target address, and access the cache for the target instructions.
	showcase.netins.net /web/stanlass/c2brnch.htm (447 words)

	Result Analysis and Discussion
		The last two columns list the number of taken conditional branches and their percentage with respect to the total number of conditional branches traced from the third column.
		The x-axis shows for a particular branch the percentage of executed branches that are taken.
		This result also indicates that the branch behavior is the most important parameter in determining the prediction accuracy of each scheme.
	www.cs.ucdavis.edu /~su/Berkeley/cs252/result.html (2268 words)

	Branch and Loop Reorganization to Prevent Mispredicts - Intel® Software Network
		Static branch prediction is used by the microprocessor the first time a conditional branch is encountered, and dynamic branch prediction is used for succeeding executions of the conditional branch code.
		Static branch prediction is used when there is no data collected by the microprocessor when it encounters a branch, which is typically the first time a branch is encountered.
		It is best to use a conditional branch in the manner that the static predictor expects, rather than adding these branch hints.
	www.intel.com /cd/ids/developer/asmo-na/eng/66779.htm?page=3 (304 words)

	Conditional branch -- Facts, Info, and Encyclopedia article (Site not responding. Last check: 2007-10-10)
		Conditional branch -- Facts, Info, and Encyclopedia article
		This is a common method in (Creating a sequence of instructions to enable the computer to do something) computer programming.
		Conditional branches are often issued in (additional info and facts about speculative execution) speculative execution, primarily because there is no simple solution to predict which branch will be selected when the condition is evaluated.
	www.absoluteastronomy.com /encyclopedia/c/co/conditional_branch.htm (242 words)

	final-paper
		The second level is the branch behavior for the last s occurrence of the specific pattern of these k branches.
		The prediction of a conditional branch is based on the branch's own history and the pattern history bits in the global pattern history table entry indexed by the content of the branch's history register.
		The basic principle of the skewed branch predictor is to use several branch-predictor banks, but to index them by different and independent hashing functions computed from the same vector V of information (e.g., branch address and global history).
	www.eecis.udel.edu /~wzhou/course/cis662/paper.html (2652 words)

	Branch prediction - Computing Reference - eLook.org
		When a branch instruction is executed, its address and that of the next instruction executed (the chosen destination of the branch) are stored in the Branch Target Buffer.
		When the prediction is correct (and it is over 90% of the time), executing a branch does not cause a pipeline break.
		An extension of the idea of branch prediction is speculative execution.
	www.elook.org /computing/branch-prediction.htm (132 words)

	Chapter 4 Notes
		Conditional Branch - Execution is nonsequential, instead of executing the next sequential instruction, a branch is made conditionally to another instruction address.
		Conditional branching tests whether a condition is true, if true the branch to a label is made, otherwise the next sequential instruction is executed.
		If the condition is true, execution sets the IP to the offset of label A: by IP = IP + F2 Problems - The problem that occassionally occurs is when a conditional jump is attempted that is too far from the destination label, beyond -128 to 127 bytes away.
	homepages.ius.edu /RWISMAN/C335/HTML/Chapter4.htm (2589 words)

	Interprocedural Conditional Branch Elimination (Site not responding. Last check: 2007-10-10)
		The existence of statically detectable correlation among conditional branches enables their elimination, an optimization that has a number of benefits.
		This paper presents techniques to determine whether an interprocedural execution path leading to a conditional branch exists along which the branch outcome is known at compile time, and then to eliminate the branch along this path through code restructuring.
		The technique consists of a demand driven interprocedural analysis that determines whether a specific branch outcome is correlated with prior statements or branch outcomes.
	www.cs.berkeley.edu /~bodik/research/pldi97a.html (261 words)

	ipedia.com: Speculative execution Article (Site not responding. Last check: 2007-10-10)
		It is useful only when early execution consumes less time and space than later execution would, and the savings are enough to compensate, in the long run, for the possible wasted effort of computing a value which is never used.
		Modern pipelinedd microprocessors use speculative execution to reduce the cost of conditional branch instructions.
		When a conditional branch instruction is encountered, the processor guesses which way the branch is most likely to go (this is called branch prediction), and immediately starts executing instructions from that point.
	www.ipedia.com /speculative_execution.html (360 words)

	Assembler Language Reference - bc (Branch Conditional) Instruction
		If the Absolute Address bit (AA) is 0, then the branch target address is computed by concatenating the 14-bit Branch Displacement (BD) and b'00', sign-extending this to 32 bits, and adding the result to the address of this branch instruction.
		The Branch Option field (BO) is used to combine different types of branches into a single instruction.
		In the PowerPC Architecture, the y bit provides a hint about whether a conditional branch is likely to be taken.
	publibn.boulder.ibm.com /doc_link/de_DE/a_doc_lib/aixassem/alangref/bc.htm (550 words)

	Introduction (Site not responding. Last check: 2007-10-10)
		In order to increase the processor performance, some branch prediction techniques are proposed for conditional branches [1,2,3,4,5].
		A predictor uses a counter in PHT to predict the direction of conditional branch by using the most significant bit of the counter.
		The branch address and branch history were used to index the pattern history table.
	www.umiacs.umd.edu /users/hismail/818K/node1.html (642 words)

	Program Control Instructions in Assembly Language
		Branch is usually an indication of a short change relative to the current program counter.
		Jump is usually an indication of a change in program counter that is not directly related to the current program counter (such as a jump to an absolute memory location or a jump using a dynamic or static table), and is often free of distance limits from the current program counter.
		Condition codes are the list of possible conditions that can be tested during conditional instructions.
	www.osdata.com /topic/language/asm/progcont.htm (2397 words)

	Assembler Language Reference - bc (Branch Conditional) Instruction
		If the AA is 1, then the branch target address is BD concatenated with b'00' sign-extended to 32 bits.
		bit provides a hint about whether a conditional branch is likely to be taken.
		The branch is very likely not to be taken.
	publib16.boulder.ibm.com /pseries/Ja_JP/aixassem/alangref/bc.htm (715 words)

	[No title] (Site not responding. Last check: 2007-10-10)
		Any conditional branch instruction that is not a pseudo-instruction.
		The conditional branch and unconditional jump instructions are described on pages A-61 through A-65.
		The example on page 150 gives the instructions generated by an assembler if the branch label of a conditional branch is outside this range.
	cs.gmu.edu /~rsingh9/365/s03/a1.html (217 words)

	Branch and Loop Reorganization to Prevent Mispredicts - Intel® Software Network
		A problem with this approach arises, however, due to conditional branches.
		Branch prediction is what the processor uses to decide whether to take a conditional branch or not.
		Getting this information as accurately as possible is important, as an incorrect prediction (mispredict) will cause the microprocessor to throw out all the instructions that did not need to be executed and start over with the correct set of instructions.
	www.intel.com /cd/ids/developer/asmo-na/eng/dc/windows/66779.htm (248 words)

	Link-Time Optimization Techniques for Eliminating Conditional Branch Redundancies
		This paper discusses the discovery and elimination of redundant conditional branches in the context of a link-time optimizer, an optimization that we call Conditional Branch Redundancy Elimination (CBRE).
		Our experiments show that around 20% of conditional branches in a program can be considered redundant because their outcomes can be determined from a previous short dynamic execution frame.
		Our results show that around 5% of the conditional branch redundancy detected can indeed be eliminated, which translates into execution time reductions of around 4%.
	csdl2.computer.org /persagen/DLAbsToc.jsp?resourcePath=/dl/proceedings/&toc=comp/proceedings/interact/2004/2061/00/2061toc.xml&DOI=10.1109/INTERA.2004.1299513 (228 words)

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