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Topic: Core memory

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  Magnetic core memory   (Site not responding. Last check: 2007-11-07)
Core memory was part of a family of related technologies, now largely forgotten, which exploited magnetic properties of materials to perform switching and amplification.
Early core memory systems had cycle times of about 6µs, which had fallen to 1.2µs by the early 1970s, and by the mid-70s it was down to 600ns (0.6µs).
A characteristic of core was that it is current-based, not voltage-based.
www.sciencedaily.com /encyclopedia/magnetic_core_memory   (1748 words)

 Core rope memory - Wikipedia, the free encyclopedia
Core rope memory is a form of read-only memory (ROM) for computers, first used by early NASA Mars probes and then in the Apollo Guidance Computer (AGC) designed by MIT and built by Raytheon.
Contrary to ordinary magnetic core memory, which was used for RAM at the time, all the ferrite cores in a core rope are permanently magnetized in one direction.
The signal from a wire passing through a given core is interpreted as a binary "one" while a wire that bypasses the core is read as a "zero".
en.wikipedia.org /wiki/Core_rope_memory   (194 words)

 Core memory   (Site not responding. Last check: 2007-11-07)
Core memory has been in use until recently for special purposes, because it retains the information when the power is switched off, and it is resistant against radiation.
The physical basis of core memory is the fact that a current sent along a wire passing through a ferrite core sets a persisting core magnetization, if the current exceeds a certain threshold.
Core memories were often organized as a planar matrix, the 'write' wire being split up into two wires (row, column) each carrying half of the threshold switching current.
www.science.uva.nl /faculteit/museum/CoreMemory.html   (643 words)

 !401 Core memory
Core memory is consists of thousands of small rings (cores) made of ferrite (iron dust in a binder), strung together on a matrix of fine wires.
One of the quirks of core memory is that the process of reading data out of it also erases the data in the cores, and so the contents of a memory location must be immediately written back each time it is read.
Core memory requires fairly large current pulses to magnetize the cores, and therefore many of boards involve power circuitry with large heatsinks.
members.optushome.com.au /intaretro/1401Core.htm   (649 words)

 Edward Shanley Core Memory Interview   (Site not responding. Last check: 2007-11-07)
The core would be coated with a chemical so the individual core’s adhesion to the silicon rubber sheets used in the stack construction.
The cores would be placed in a metal sheet, with spaces etched into it to hold the individual cores, in a double herring bone pattern.
After each core had an “x” and “y” wire put through it a third “z” sense wire was put through the inner diameter the ends would be soldered to PC stack board.
www.pdp8.com /id1.html   (735 words)

 Multiple event hardened core memory - Patent 4464752
Memory word loss may be obviated in a random access memory without the need for redundant storage, in the case of the fixed data, by the use of the plated wire type non-destructive readout memory.
In the case of the magnetic core memory, however, the word desired in each read operation must be restored in a subsequent write operation, so that the affected word may be lost during the presence of nuclear radiation.
In the case of the core memory, however, the corrective measures must be taken with respect to words being read or written during the nuclear event.
www.freepatentsonline.com /4464752.html   (4962 words)

 Core Memory
If the memory location is to contain a 0, the sense/inhibit line is driven with sufficient current to neutralise the effect of the XY lines and the memory location will be unaffected and stay in the 0 state.
If the memory location is to contain a 1, the sense/inhibit line is not driven, and the XY lines will flip the memory core into the 1 state.
Core memory, being a magnetic device, is susceptible to the effects of interference.
www.psych.usyd.edu.au /pdp-11/core.html   (983 words)

 Core Memory   (Site not responding. Last check: 2007-11-07)
MIT invented the core memory, which uses the persistence of direction of magnetic flux in a doughnut-shaped carbon ring to represent 0 or 1.
Cores retain their magnetization, so that the cores not read do not have to be regenerated, a critical operation in earlier memories, as storage tubes.
By 1974 the cost of core memory was down to 1 cent/bit, but semiconductor memory had reached the same price then, and continued to go down in price rapidly, replacing core memory for most purposes.
www-db.stanford.edu /pub/voy/museum/pictures/CoreMemory.html   (818 words)

 Core memory with return drive scheme - Patent 4523302
The core memory according to claim 1 or 3 above, wherein the common ends of the X conductors are coupled to nothing other than the paths through the X conductors themselves and the common ends of the Y conductors are coupled to nothing other than the paths through the Y conductors themselves.
Furthermore, in a conventional core memory, the sense line and parallel drive line are separated by the orthogonal or X drive line passing between them to reduce inductively coupled drive current noise.
A core array 1280 has magnetic memory cores 1282 inductively coupled by the Y drive conductors 1272 with each Y drive conductor 1272 inductively coupling all of the cores 1282 in a column.
www.freepatentsonline.com /4523302.html   (9039 words)

 Livid's Lividict - ferrite core memory   (Site not responding. Last check: 2007-11-07)
A third "sense" wire, passed through the core and, if the magnetisation of the core was changed, a small pulse would be induced in the sense wire which could be detected and used to deduce the core's original state.
Some core memory was immersed in a bath of heated oil to improve its performance.
Core memory was rendered obsolete by {semiconductor} memory.
livid.3322.org /lookup/ferrite%20core%20memory.html   (316 words)

 Core Memories
Core was so expensive that the entire system, the computer that ran a 40,000 student campus, had but a pathetic 64k - with no disk storage.
The trick is to flip the magnetic field of the cores -- one direction is a "one"; the opposite field indicates a "zero".
The core plane is an array of vertical and horizontal wires with a bead at each intersecting node.
www.avocetsystems.com /company/articles/magazine/core-mem.htm   (1439 words)

 Core Memory   (Site not responding. Last check: 2007-11-07)
The IBM 2361 Core Storage Module housed 16K bytes of core memory.
The one core in the center of the figure is switched, however, by the coincidence of the two currents.
A 4th wire was the 'inhibit' wire used prevent some core from flipping' I have an old 4k 1401 memory core sitting out on my work bench gathering dust for the last 25 years.
www.columbia.edu /acis/history/core.html   (317 words)

 A 110-Nanosecond Ferrite Core Memory
The memory has a capacity of 8192 words, 72 bits per word, and has a cycle time of 110 nanoseconds and an access time of 67 nanoseconds.
The storage devices are miniature ferrite cores, 0.0075 by 0.0123 by 0.0029 inches, and are operated in a two-core-per-bit destructive read-out mode.
The design criteria and operational characteristics of the core, and the approach taken on the bit line recovery problem, are also presented.
domino.research.ibm.com /tchjr/journalindex.nsf/0/21e759593b636e4e85256bfa00683f81?OpenDocument   (122 words)

 Core memory history from the PCmuseum
Each memory plane had a fine mesh of wires with tiny magnetic "doughnuts" or rings where the lace of wires crossed.
The core memories consisted of a tiny magnetic doughnuts (1024 in this case).
One defective or broken core (and they are very fragile), would entail removing the wires associated with that core, removing the core, usually a chunk at a time, and inserting a new core in its place.
www.fortunecity.com /marina/reach/435/coremem.htm   (698 words)

 Core War Article #1
Nowadays memory elements are fabricated on semiconductor chips, but the active part of the memory system where a program is kept while it is being executed, is still often referred to as core memory, or simply core.
Core War was inspired by a story I heard some years ago about a mischievous programmer at a large corporate research laboratory I shall designate X. The programmer wrote an assembly-language program called Creeper that would duplicate itself every time it was run.
The memory array differs from most computer memories in its circular configuration; it is a sequence of addresses numbered from 0 to 7999 but it thereupon rejoins itself, so that address 8000 is equivalent to address 0.
www.koth.org /info/akdewdney/First.htm   (3820 words)

 [No title]   (Site not responding. Last check: 2007-11-07)
These two states corresponded to a digital '1' or '0.' Core memory is 'non-volatile,' meaning it retains its contents even with power removed.
For this and other technical reasons, it is still used on some spacecraft today.”  After core memory in 1957 plated wire memory was developed at Bell Laboratories.
  It is similar to core memory in that is it is ‘non-volatile,’ and it is not sensitive to radiation.
pigseye.kennesaw.edu /~astowell/index5.htm   (222 words)

 BDTI - SGS-Thomson D950-CORE
The core is foundry-captive and is intended to be used in application-specific integrated circuits (ASICs) fabricated by SGS-Thomson.
Each of the three memory spaces uses two 16-bit buses that are extended off-core to address up to 64 Kwords of off-core memory each.
Each of the two data memory spaces has an address generator that provides two address registers and four modifier registers, which are used for post-modification, indexed addressing, and modulo addressing.
www.bdti.com /procsum/d950.htm   (336 words)

 Core Memory   (Site not responding. Last check: 2007-11-07)
The earliest core's were rather large, easily visible with the human eye, and the core's and wires were actually strung together "by girls stringing wires with long needles...".
The core memory seen below is a much later version - the core's are so tiny that I cannot even see them without magnification.
The entire core memory circuit board is 370mm X 165mm (14.5" X 6.5").
www.oldcomputers.net /core.html   (252 words)

 Project History: Magnetic Core Memory   (Site not responding. Last check: 2007-11-07)
Jay Forrester, who was head of the Whirlwind computer project, invented core memory at MIT in the late 1940s.
Semiconductor memories largely replaced magnetic cores in the 1970s, but they remained in use for many years in mission-critical and high-reliability applications.
This project history will work primarily with the core memory collection in the MIT archives, one of the richest sets of documentation for a particular invention that exists.
web.mit.edu /6.933/www/core.html   (305 words)

 Mission Critical Linux - In Memory Core Dump   (Site not responding. Last check: 2007-11-07)
Core dump systems allow for the state of a machine to be saved at crash time for later analysis.
Often, a core dump system will write relevant data to a swap partition at crash time.
If you're currently using Mission Critical Linux's In-memory core dump system, make sure you read the INSTALL file before upgrading, as it contains important information regarding backwards compatibility issues.
oss.missioncriticallinux.com /projects/mcore   (181 words)

 QDR-2 SRAM Memory Interface Core   (Site not responding. Last check: 2007-11-07)
LSI Logic's QDR2 core provides an easy physical layer interface between the customer logic of the ASIC and the data and address busses of the QDR-2 SRAM memory.
The datapath hardmacro is 18 bits wide and multiple of these cores can be used in parallel to handle data bus widths of 36 bits (2 hardmacros) and 72 bits (4 hardmacros).
The main function of the cores is to enable memory READ and WRITE operations and provide an easy interface for the customer logic in the single data rate domain thereby taking the pain away from handling the tight timing margins associated with high performance double data rate QDR2 SRAM interfaces.
www.lsilogic.com /products/qdr_2_sram_memory_interface_core   (243 words)

 LIS Course Notes - Magnetic Core Memory
In the UNIX and Linux world, the diagnostic file containing the memory dump is still named "core".
Voltage applied along the grid wires changed the polarity of the cores.
Thanks to Keith Thomas for suggesting that the machine for which this particular memory was most likely designed, may have used a 24-bit word length, with 1 parity bit for error detection and correction, hence all the multiples of 25.
valinor.ca /computing/corememory.html   (197 words)

 X-bit labs - Articles - AMD Athlon 64 Processors on E Core: Memory Controller Peculiarities in Detail (page 6)
The memory controller of these CPUs is a part of the processor core that is why the CPU doesn’t use any busses or bus protocols to address the memory controller.
It means that the memory frequency in Athlon 64 based systems is not determined by the clock generator frequency or bus frequency but is based on the CPU clock rate and its clock frequency multiplier.
The memory clock frequency is only determined by the CPU clock rate and the corresponding divider that is why Athlon 64 processors with different clock frequencies set slightly different working frequencies for the memory modules in the system.
www.xbitlabs.com /articles/cpu/display/athlon64-e3-mem_6.html   (838 words)

 Energy Citations Database (ECD) - Energy and Energy-Related Bibliographic Citations
A word-arranged magnetic-core memory is designed for use in a digital computer utilizing the reverse or back current property of the semi-conductor diodes to restore the information in the memory after read-out.
In order to retain the information in the memory after read-out it is then necessary to provide a means to return the switched cores to their states before read-out.
This pulse combines with the reverse current pulses of diodes for each column in which a core is switched during read-out to cause the particular cores to be switched back into their states prior to read-out.
www.osti.gov /energycitations/product.biblio.jsp?osti_id=4794790   (219 words)

 A 0.7-Microsecond Ferrite Core Memory
A two-dimensional array organization and partial switching of toroidal cores were employed in the design of this low-power, high-speed memory.
The memory features a unique combination of a current-steering diode matrix and a load-sharing magnetic switch for an economical and high-performance drive system.
The operating memory has a storage capacity of 73,728 bits and executes instructions reliably up to a repetition rate of 1.47 mc.
domino.research.ibm.com /tchjr/journalindex.nsf/0/64879bd1203e30e285256bfa00683df1?OpenDocument   (113 words)

 CAST NFlashCntl NAND Flash Memory Controller Core
The core has been rigorously verified and provides competitive speed and area results, for example, with a 0.18µ ASIC process it uses just 5,817 gates and runs at 333 MHz.
Access to the memory is always through this block; the master has no direct connection with the memory.
The core as delivered is warranted against defects for three years from purchase.
www.cast-inc.com /cores/nflashcntl/index.shtml   (537 words)

 SFBG S.F. Life | February 7, 2001 | techsploitation   (Site not responding. Last check: 2007-11-07)
Although in my memory the Apple II will always look like a Porsche, these crud-colored boxes with their cloudy screens reminded me that the mid '80s are practically medieval now.
Lee and Chris showed us some of the earliest core memory, huge poster-size sheets of wires coiled tightly together in webs where three square inches might hold 12 bytes.
As we drove home, I kept thinking about core memory and how so much of what we do in the "information economy" depends on what grew out of those tiny electromagnetic wires that not so long ago lit up the faces of mainframes.
www.sfbg.com /SFLife/tech/45.html   (770 words)

 EETimes.com - Sonics core optimizes memory usage of SoCs   (Site not responding. Last check: 2007-11-07)
The MemMax Memory Scheduler gives designers control over memory subsystems that are now awkwardly shared by the multiple, contentious processors typically used in SoC designs, said Ed Smith, vice president of marketing at Sonics.
The scheduler core is positioned between any memory controller interfaced with the Open Core Protocol and the Sonics SiliconBackplane MicroNetwork.
Bundled in each packetized core, Smith said, is information such as thread identifiers and data on how much access the core needs to the off-chip RAM to work effectively.
www.eetimes.com /story/OEG20020306S0030   (727 words)

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