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Topic: DMA controller

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Direct memory access

	DMA and Embedded Systems
		Once the entire transfer is complete the DMA controller may quietly go to sleep, or it may restart the transfer when the I/O is ready for another block, or it may signal the processor that the action is complete.
		To summarize, the processor programs the DMA controller with parameters about the transfers, the controller tri-states the CPU and moves data over the CPU bus, and then when the entire block is done the controller signals completion via an interrupt.
		The DMA controller gains exclusive access to the bus for the duration of the transfer, during which time the program is effectively shut down.
	www.avocetsystems.com /company/articles/magazine/adma.htm (2357 words)

	Patent 5613162: Method and apparatus for performing efficient direct memory access data transfers
		The DMA controller also includes a second set of independently programmable DMA control registers which identify a second source, a second destination and a second quantity of data to be transferred between the memory and the I/O device via the I/O bus.
		The DMA controller transfers data between the first data buffer and the second data buffer as bursts of data at a high data rate and then releases the I/O bus while data is transferred between second data buffer and the I/O device at the second data rate.
		The DMA controller controls the first set of DMA control registers and the first data buffer independently of the second set of DMA control registers and the second data buffer so that data transferred between the memory and the first I/O device is interleaved with data transferred between the memory and the second I/O device.
	www.freepatentsonline.com /5613162.html (11539 words)

	Patent 4975832: Microcomputer system with dual DMA mode transmissions
		The DMA controller can cause the CPU either to be electrically coupled to the bus system for programmed CPU data transmission between the I/O device and the memory, or to be uncoupled therefrom for DMA data transmission therebetween.
		The efficiency of DMA data transmission is gained, however, at the sacrifice of the response of the CPU, the latter being held isolated from the bus system during the extended period of DMA transmission.
		The DMA controller circuit 14 functions to selectively set the microcomputer 10 in the DMA mode such that the data is sent directly between the RAM section of the memory 13 and the I/O device 17, bypassing the CPU 12.
	www.freepatentsonline.com /4975832.html (4066 words)

	Patent 5056010: Pointer based DMA controller
		Hence, the DMA controller must ascertain whether the buffer memory is empty or full when the host is to transfer data on the one hand, and to assure that there is a complete sector of data to be written into the disk.
		Furthermore, the DMA controller generates address signals that are necessary for the host and the disk controller to access a specific buffer memory location so that the data can be transferred to or from the buffer memory.
		The DMA controller 5 further comprises a comparator 34, one side of which is connected to the HP 20 and the DP 21 and the other side of which is connected to the CP 23 and the GP 22.
	www.freepatentsonline.com /5056010.html (6342 words)

	DMA Controller for AHB (Site not responding. Last check: 2007-10-20)
		The DMA controller then re-arbitrates for bus ownership to write data from the local buffer to the destination address on AHB.
		The DMA controller can be programmed to use single, burst of 4, or burst of 8 words to transfer data.
		The DMA controller relinquishes the AHB and re-arbitrates for the bus again between each burst transfer so that other devices on the bus receive their fair share of memory bandwidth on the AHB.
	www.altera.com /products/ip/iup/peripherals/m-eur-ahb-dma.html (753 words)

	EP1217602 (Site not responding. Last check: 2007-10-20)
		Accordingly, the DMA controller inputs a continuous data flow comprising image frames from the memory 102 to the display unit 116.
		In accordance with the invention, said synchronization signals are led by feedback to the control system of the display system, particularly to the MCU, from which a control command, generated on the basis of the synchronization signals, is further transferred to the DMA controller for storing a new image frame in the frame buffer.
		Advancing the update command of the DMA controller suitably allows interference in the update of image frames caused by possible delays on the transfer bus and, at the same time, the coincidence of the update of the screen and the update of the frame buffer on the same line to be avoided.
	swpat.ffii.org /pikta/txt/ep/1217/602 (6891 words)

	DMA Controller
		DMA channels 0 and 4 are active in MCA systems and can be reprogrammed by an OS to respond to arbitration levels 8 thru 15.
		Each DMA port is assigned an arbitration level to which it responds when that level recieves control of the bus.
		DMA levels 0-7 are assigned to arb levels 0-7 during boot.
	ohlandl.ipv7.net /parts/DMA_Controller.html (673 words)

	CHRP ISA DMA Controller Device Binding (Site not responding. Last check: 2007-10-20)
		DMA Controller 1 provides four DMA channels (designated channels 0-3) which are capable of 8 bit DMA transfers.
		Controller 2 provides four DMA channels (designated channels 4-7) of which channels 5-7 are capable of 16 bit DMA transfers.
		Channel 4 is used for cascading DMA Controller 1 to DMA Controller 2 and is unusable for data transfer with an ISA device.
	bananajr6000.apple.com /1275/bindings/devices/html/isa-dma.html (754 words)

	DMA: What it Is and How it Works
		The second DMA controller (4, 5, 6, and 7) moves 16-bits from two adjacent memory locations in each transfer, with the first byte always coming from an even-numbered address.
		The two controllers are identical components and the difference in transfer size is caused by the way the second controller is wired into the system.
		The 8237 DMA is known as a ``fly-by'' DMA controller.
	www.pl.freebsd.org /handbook/handbook320.html (465 words)

	DMA
		The Direct Memory Access (DMA) is implemented in the ISA bus through the DMA controller (actually, two of them but that is an irrelevant detail).
		To make the early ISA devices simple and cheap the logic of the bus control and address generation was concentrated in the DMA controller.
		Length of 0 is not allowed: the DMA controller will understand it as 64KB while the kernel code will understand it as 0 and that would cause unpredictable effects.
	www.freebsd.org /doc/en_US.ISO8859-1/books/arch-handbook/isa-driver-dma.html (816 words)

	Eureka Technology - AMBA AHB Direct Memory Access (DMA) Controller IP core
		The DMA controller then re-arbitrates for bus ownership to write data from the local buffer to the destination address on AHB bus.
		Non-buffered DMA transfer is designed for transferring data between the AHB bus and the channel’s dedicated I/O port.
		The DMA controller relinquishes the AHB bus and re-arbitrates for the bus again between each burst transfer so that other devices on the bus receive their fair share of memory bandwidth on the AHB bus.
	www.eurekatech.com /products/arm/ep246.htm (789 words)

	DMA
		Whenever a DMA channel is active, the contents of that latch are written to the address bus and kept there until the DMA operation for the channel ends.
		Once the DMA has moved the data into this buffer, the operating system will then copy the data from the buffer to the address where the data is really supposed to be stored.
		The slave DMA controller then transfers data for the DMA channel that requested it (0, 1, 2 or 3), or the slave DMA may grant the bus to a peripheral that wants to perform its own bus-mastering, such as a SCSI controller.
	www.freebsd.org /doc/en_US.ISO8859-1/books/developers-handbook/dma.html (3379 words)

	DMA : Computer Buyers’ Guide (Site not responding. Last check: 2007-10-20)
		The ordinary slow style DMA is called 3rd party DMA because the DMA controller acts as a third party to mediate between two other devices (usually RAM and a peripheral).
		Because these built-in DMA controllers are so slow and so ineptly designed, sometimes a PCI card or ISA SCSI card will provide its own replacement high speed DMA controller that runs at full bus speed.
		The standard DMA controller is so incredibly slow that, PIO is faster for hard disk access.
	www.mindprod.com /bgloss/dma.html (347 words)

	Nintendo Fire - Cheat Codes for Nintendo DS, GameCube, Game Boy, Super NES, NES, GBA, N64 - Game Genie Codes and ... (Site not responding. Last check: 2007-10-20)
		Worlds of Wonder was successful: the NES had sold over 20 million units in the US alone by the end of its production run.
		Having Super Mario Brothers on the package meant success for Nintendo, whom controlled the market with a 10 to 1 market share, due to the fact that many video games published by third parties went to the NES.
		* 2 seven pin controller ports in the front of the machine * 1993 re-release does not have RCA composite output plugs.
	www.nintendofire.com /Nintendo-Encyclopedia/NES.html (1693 words)

	A Guide to Adapters and I/O units.
		The IRQ controller asks the CPU permission to use the bus, to send the byte to wherever.
		With DMA, this "intelligence" is assigned to a DMA controller on the system board.
		The DMA system can result in conflicts between two units on the bus, if they have requested the same DMA channel.
	www.karbosguide.com /hardware/module5a3.htm (1302 words)

	Ultra ATA FAQ
		DMA increases speed by using the DMA controller to manager the data transfer rather than the processor.
		Bus Mastering DMA allows the interface card, or drive controller, to manage the transfer of data from the drive directly to the system’s memory.
		Ultra ATA compatible motherboards and controllers were phased in when the Pentium MMX processors were introduced to the market.
	www.seagate.com /support/kb/disc/ultra_ata_faq.html (773 words)

	[No title] (Site not responding. Last check: 2007-10-20)
		Since the DMA controller does everything in 64k blocks, it is best to try to align the buffer to the segment edge, I.e.
		This register controls the mode of transfer, it will vary upon the device which we want to transfer to.
		Now that we have correctly set up the DMA controller for the transfer, we can enble the channel.
	www.textfiles.com /computers/DOCUMENTATION/dma.txt (570 words)

	DMA controller - a reference guide from Electronicstalk
		DMA controller - a reference guide from Electronicstalk
		We see from your search that you're looking for information on the term "DMA controller", and we have a large number of manufacturers' news stories and technical articles here on Electronicstalk which will be of interest.
		A couple of weeks before, we featured the news story Frugal MCU turns to ZigBee networking from Texas Instruments: "Texas Instruments has collaborated with Ember Corp to unveil the world's lowest power consuming ZigBee networking and microcontroller (MCU) platform.".
	www.electronicstalk.com /guides/dma-controller.html (290 words)

	DMA Controller (Site not responding. Last check: 2007-10-20)
		Figure 1 shows the block diagram for the DMA controller megafunction.
		The DMA controller megafunction is designed for data transfer in different system environments.
		Each DMA channel can be programmed for various features, such as transfer size, synchronized and unsynchronized transfer control, transfer priority, interrupt generation, memory and I/O address space, and address change direction.
	www.altera.com /products/ip/iup/memory/m-eur-dma-cont.html (234 words)

	Re: PCI DMA info require
		Hi, > hi all, > i need some info as to how DMA is used by > PCI devices ex.
		I think that the DMA is performed by the network card dma controller (pci dma controller).
		While reception, the network would automatically perform DMA from the local buffer (of the network card) to the location which we had specified in step 1.
	mail.nl.linux.org /kernelnewbies/2004-03/msg00053.html (166 words)

	Ultra DMA, Controller Card and Modes Question
		My mobo is an Intel mp440bx which I believe can only handle DMA mode 2 with the last of the bios revisions - the 4m4pbox1.15A.033.
		A new IDE controller card capable of DMA mode 5 would work, but I doubt that you would see enough improvment in performance to justify buying and installing one.
		Yes, the controller card will add faster ATA support, and yes, with a newer drive, it is worth the cost - most drives will now deliver in the 60s (MBps), about double what your onboard drive interface can handle.
	hardware.mcse.ms /showthread.php?goto=lastpost&threadid=138641 (865 words)

	Synopsys Synthesizable Intel 8237A DMA Controller
		The Intel 8237A is a simple DMA controller.
		In order to simplify using this controller for educational purposes, many of the advanced features have been removed.
		The provided design is also synthesizable through Synopsys dc_shell and a testbench is also provided to demostrate the programming and DMA operations.
	www.edaboard.com /ftopic12555.html (191 words)

	WEB HOSTING : DAC960 : 2.6.8 (Site not responding. Last check: 2007-10-20)
		* request sense and scatter gather dma structures are free.
		Aggregate the space needed for the controller's memory mailbox and
		controllers, appears to work quite well with this driver.
	www.oxxus.net /host/2.6.8/hosting-DAC960.htm (1705 words)

	Sound Troubles (Site not responding. Last check: 2007-10-20)
		PCI has no ISA DMA support (in the form of DREQ/DACK signals and a seperate DMA controller).
		Lots of DOS software programs the hardware directly, and they expect a DMA controller to program as well as the soundcard's registers.
		The problem is therefore in how to make a PCI soundcard emulate the ISA DMA controller, but only for that DMA channel (so it doesn't interfere with true ISA cards communicating with the real ISA DMA controller).
	www.mameworld.net /emuadvice/pci.html (750 words)

	dma controller (Site not responding. Last check: 2007-10-20)
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	www.zanzibarlavilla.it /flm%5Fzanzibar/dma_controller.asp (310 words)

	Programmer's Technical Reference for MSDOS and the IBM PC
		The initialization portion of COMMAND.COM follows the resident portion and is given control during the bootup procedure.
		An initialization routine is included in the resident portion and assumes control during startup.
		If your code incorporates specific port addresses for video or system board control it would be wise to have your application determine the machine type and video adapter and address the ports as required.
	www.o3one.org /hwdocs/bios_doc/dosref22.html (8658 words)

	ARM + DMA controller support
		Even though I am an experienced user of ARM, I was not able to find a way to use a DMA model (easily).
		I do not want to write a new DMA model and put it in the armulator configuration file.
		I am also using Code Composer TI which has very nice support for the DMA controller (it has some DMA macros, functions and a nice simulator).
	www.edaboard.com /viewtopic.php?p=288785 (232 words)

	The Linux Ultra-DMA Mini-Howto: Problems (Site not responding. Last check: 2007-10-20)
		The real work involved in setting up the chips for DMA transfers is done mostly by the BIOS of each motherboard.
		For example, the ASUS SP-97V motherboard with its original BIOS (Rev. 1.03) would malfunction with the modified Linux driver in both DMA mode 2 and UDMA modes; it would work well using PIO mode 4, or under Windows 95 in all modes.
		What this tells us is that the BIOS sets up the DMA controller with specific timing parameters (active pulse and recovery clock cycles).
	www.linuxpowered.com /LDP/HOWTO/Ultra-DMA-9.html (379 words)

	Re: hpt366 ultra dma controller
		In Reply to: Re: hpt366 ultra dma controller posted by Mwm on October 28, 2001 at 19:02:50:
		(you might have to flash your bios) I managed to get xp to load and it even recognized both controllers after i went back into my bios and turned udma66 back on.
		P.S. i've been working on this problem for 3 weeks now and this is the first i've heard about the default xp setting in ther reg...
	www.driverforum.com /controller3/645.html (399 words)

	SYLLABUS FOR THE WRITTEN QUALIFYING EXAMINATION
		controller design (state machine and microprogram controllers); handling of interrupts and exceptions
		Potential and actual speedup, control hazards, structural hazards, data hazards; basic techniques to deal with hazards (forwarding, stalls)
		The Database Systems syllabus covers information systems and database systems in enterprises; file organization and secondary storage structures; relational model and relational database systems; other models and data management approaches; database design principles; transactions, concurrency, and recovery; and integrity and authorization.
	www.cs.ucla.edu /classes/exams/WQEsyllabus.html (811 words)

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