| |
| | Daisychaining SPI-compatible devices |
 | | When /CS goes high, the loaded commands execute: A1 and B1 are set to zero-scale, A2 and B2 are set to midscale, and A3 and B3 are set to full-scale. |
 | | The basic sequence is as follows: During the first three command cycles, each of the three chips in the daisychain receives a command in its shift register. |
 | | The commands for IC1, IC2 and IC3 are 0xB000, 0xBFF8 and 0xBFF8, respectively, loading input register B1 with midscale data, input register B2 with full-scale data and input register B3 with full-scale data, while leaving the D/A converter registers and outputs unchanged. |
| www.embedded.com /shared/printableArticle.jhtml?articleID=193002306 (1390 words) |
|