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| | Data communication arrangement with embedded matrix switch - Patent 4885741 |
 | | Data signals at various bit rates ranging from 2.4 Kb/s to 56 Kb/s are received from, and applied to, data terminal equipment such as CRT terminals, personal computers, etc., by way of the various access module ports. |
 | | In operation, data signals from the various pieces of data terminal equipment are routed from the associated cable 145 and connector 143 over a path which includes any desired number (including zero) of application modules and, at the end of the path, a predetermined data set, i.e., modem or DSU. |
 | | The latter include, for example, whether a particular data set is to use internal or external timing; the number of bits to be transferred per time slot occurrence (latency); whether the reversing of various EIA leads, referred to as "frogging," is desired; or whether the device is to be part of a digital bridge. |
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