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Topic: Data strobe encoding

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	Data strobe encoding - Wikipedia, the free encyclopedia
		Data strobe encoding (or D/S encoding) is an encoding scheme for transmitting data in digital circuits.
		These have the property that either Data or Strobe changes its logical value in one clock cycle, but never both.
		Data strobe encoding is used on the signal lines in the IEEE 1394 (aka FireWire 400) system.
	en.wikipedia.org /wiki/Data_strobe_encoding (135 words)

	[No title] (Site not responding. Last check: 2007-10-26)
		At step 630, data transmission is initiated on a clock edge of an even clock cycle, which coincides with the issuance of the data strobes on the even clock cycle.
		For purposes of simplification of explanation, the data communicated between the memory 802, processor 803 and the memory controller 805 is shown to be transmitted through the interface/control logic 834; however, it is contemplated that data may be transmitted directly between the queues and the memory 802 and processor 803.
		A bus comprising a plurality of bus lines configured to convey device configurable data from a first device to a second device during transmission of a request and further configured to convey the device configurable data from the second device to the first device during transmission of a reply to the request.
	www.wipo.int /cgi-pct/guest/getbykey5?KEY=99/15980.990401&ELEMENT_SET=DECL (8344 words)

	IEEE 1284 - Updating the PC Parallel Port - Tutorial - Development Library - National Instruments
		Data written to the Auto Address Strobe register is placed on the parallel port data lines followed by an automatic active low pulse on the ASTROBE* line.
		Data written to any of the Auto Data Strobe registers is placed on the parallel port data lines followed by an automatic active low pulse on the DSTROBE* line.
		The ECP Address and Data FIFOs contain at least 16 bytes and are used in both the forward and reverse directions for smooth data flow and improved data transfer rates.
	zone.ni.com /devzone/conceptd.nsf/webmain/0989d3d9dafae64e8625680400679736?OpenDocument (2948 words)

	Device and method for programming critical hardware parameters - Patent 5220673
		This applies to the case when both address and data are 8 bit wide, a High in output pin 15 is taken to mean that the lower 8 bit of the address/data lines are data and the higher 8 bits are address.
		In particular, the rising edge of the internal write strobe in the WRSTBT line 66 is set by the trailing edge of the external write signal, and the trailing edge of the internal write strobe is used to latch internal registers.
		When the internal data is to be written into a particular register, the top register 71 for example, the address of the register 71 is first decoded from the internal address bus 64 by a decoder 400.
	www.freepatentsonline.com /5220673.html (8070 words)

	Fundamentals of Firewire
		The maximum data block size for an asynchronous packet is determined by the transfer rate of the device, as specified in Table 2.
		With data strobe encoding, either the data or the strobe signal (but not both of them) change in a bit cell.
		Data strobe encoding is shown in Figure 4.
	www.embedded.com /1999/9906/9906feat2.htm (5067 words)

	Products
		Data bits to be transmitted through the cable ports are received from the Link on 2/4/8 data lines (D0-D8), and are latched internally in the RTL8801B in synchronization with the 49.152 MHZ system clock.
		During transmission, the encoded data is transmitted differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the TPA cable pair(s).
		The encoded data information is received on the TPA cable pair, and the encoded Strobe information is received on the TPB cable pair.
	www.realtek.com.tw /products/products1-2.aspx?modelid=23 (418 words)

	Interface - 1394 Technical Overview
		The backplane version operates at 12.5, 25 or 50 Mbits/sec, whereas the cable version supports data rates of 100, 200, 400, 800, and 1,600 Mbits/sec across the cable medium supported in the current standard.
		The signals transmitted on both the cable and backplane environments are NRZ with Data-Strobe (DS) encoding.
		DS encoding allows only one of the two signal lines to change each data bit period, essentially doubling the jitter tolerance with very little additional circuitry overhead in the hardware.
	focus.ti.com /analog/docs/articles.tsp?familyId=361&templateId=5&path=templatedata/cm/brc/data/200207_1394technicaloverview&articleType=brc (1033 words)

	SAR Processing for RASSP Application
		In remote sensing, SAR data of the Earth's surface from airborne and spaceborne platforms are used in applications as diverse as estimating surface wind speed, estimating ocean and ice movements, estimating terrain topography, classifying land surfaces and cartography [2],[3].
		Figure 6 illustrates the organization of the data within the 40-bit data word as it is presented to the parallel-to-serial converter for transmission over the fiber-optic link.
		Each PRI of data is preceded by a code or preamble which is duplicated in bits 3 through 16, 19 and 32 of the 40-bit data word.
	www.ll.mit.edu /llrassp/bwz/rasspcon3.html (5526 words)

	[No title] (Site not responding. Last check: 2007-10-26)
		Even in the context of a ring network, in which data propagates from one device to another around a loop or ring (and is overwritten when a device desires to insert its own data), a device on a TDMA network could transmit information (such as a digital audio sample) anytime during its assigned time slice.
		Several modes of data transmission are possible and the selected mode determines the number of lanes in a frame.
		An alternative embodiment measures data propagation times with a special timer resident in the PHY layers of both the device and the Clock Master that enables enhancing the absolute time accuracy of the network.
	www.wipo.int /cgi-pct/guest/getbykey5?KEY=01/08366.010621&ELEMENT_SET=DECL (13145 words)

	Home Toys Article (Site not responding. Last check: 2007-10-26)
		The new 1394b data encoding improvements are based on the same "8B10B" codes (a way to encode the data so that it is easier to send it over longer distances) used by Fibre Channel and Gigabit Ethernet.
		Together, the two improvements comprise what is called the Beta mode of operation (which is new and unique to 1394b) to distinguish it from the 1394-1995/1394a legacy mode's Data Strobe (DS) coding (with the data traveling on one pair of wires within the 1394 cable and the synchronizing strobe on the other pair).
		However, the 1394b encoding and decoding processes are more complicated for the chip makers to implement and require the logic and a Phase Locked Loop (PLL) to do the more complex 1394b clock and data recovery from the 8B/10B encoded stream (the legacy 1394a Data/Strobe encoding is simpler).
	www.hometoys.com /htinews/jun02/articles/drflick/1394b.htm (7013 words)

	Computer Technology Review: Serial ATA: a comparison with Ultra ATA technology - Serial ATA
		Using this technology, data is registered both on the rising and falling edges of the data strobe, halving the required strobe frequency.
		Because data is encoded using 8b/10b encoding (an 80% efficient encoding used with digital differential signaling to maintain a constant average DC bias point), the effective maximum throughput is 150MB/sec.
		Undesired analog effects associated with parallel data busses such as crosstalk, ground bounce, ringing, and clock skew have become major design constraints for the Ultra ATA interface, which is forced to maintain compatibility with legacy parallel technology.
	www.findarticles.com /p/articles/mi_m0BRZ/is_11_22/ai_98977131 (1407 words)

	FPGA FAQ comp.arch.fpga archives - messages from 50925
		The encoding is such that taking the xnor of both lines gives the serial clock.
		Use the CE pin to control the loading of data into the flip-flop" which I think could be why it doesn't work when programmed.
		Both strobe and data lines are used to recover clock which might be the reason why jitter is lower as oppposed to data and clock begin received on separate wires where there might be a systematic bias on one or the other.
	www.fpga-faq.org /archives/50925.html (6738 words)

	iApplianceWeb-OEG (Site not responding. Last check: 2007-10-26)
		A 1394b Data Analyzer from Yokogawa Corporation will be connected to the two computers to validate 1394b data transmission.
		The new 1394b PHY chip is a three-port, bilingual device that is backward compatible with 1394a devices, supporting the data strobe-encoding scheme of IEEE 1394a-2000, and the 8B/10B-encoding scheme for 1394b.
		The device is compatible with the PCI Power Management 1.1 specification, enabling active power management by the Windows operating system and integrated intelligent power management, which allows the device to automatically conserve power for power-sensitive applications like portable computers and handheld devices.
	www.iapplianceweb.com /story/OEG20010828S0039.htm (408 words)

	PDI1394P21; 3-port 400 Mbps physical layer interface
		The information published on product information pages of the www.semiconductors.philips.com or www.semiconductors.com websites is an extract from product data sheets and is for information purposes only.
		In the event of any conflict between product information pages and data sheets or deviations from information provided in the product data sheets on these product information pages, the information provided in the product data sheets shall prevail.
		The product status of the product(s) described in the product data sheet may have changed since publication of the data sheet and therefore information in datasheets on product status may be outdated.
	www.vlsi.com /pip/PDI1394P21.html (559 words)

	(WO 01/08366) APPARATUS AND METHOD FOR MEDIA ACCESS CONTROL [Repub: 21.06.2001] (Site not responding. Last check: 2007-10-26)
		In a ninth embodiment, the invention provides a method and apparatus to allocate a set of lanes in a frame containing a plurality of lanes, in a network connecting a plurality of devices.
		In an eleventh embodiment, the invention provides a method and apparatus for broadcasting device identification during startup of a device in a network connecting a plurality of devices.
		In a twelfth embodiment, the invention provides a method and apparatus for structuring the data architecture of a device read only memory (ROM) in a network connecting a plurality of devices.
	wipo.int /cgi-pct/guest/getbykey5?KEY=01/08366.010621&ELEMENT_SET=DECL (546 words)

	1394b hits home video and audio products - Home Video News - Designtechnica
		The TSB41BA3 is a three-port bilingual physical layer (PHY) device capable of speeds up to 400 Mbps, compliant with the approved version of the IEEE 1394b-2002 specification.
		The TSB41BA3 is backward-compatible with 1394a devices and supports both the data strobe encoding scheme of IEEE 1394a-2000 and the new 8B/10B encoding scheme for 1394b-2002.
		It also allows for any cable topology to be used, as loops will be automatically detected and corrected.
	news.designtechnica.com /article553.html (414 words)

	CSD February 2000 Multimedia Supplement Feature : The Firewire Connection
		The result will enable the consumer to use 1394 as a very high performance computer peripheral bus as well as a home network, with no discernible difference from the way it is currently used in the consumer electronics cluster.
		In addition, PC disk drives are approaching a 400-Mbps true data rate already, and will be needing 600-800 Mbps in the near future.
		Because the data and clock information are now encoded on a single differential pair with no dc-level signaling, there is much lower intersymbol interference, allowing the same shielded twisted-pair media specified in the 1394-1995 standard to carry a 1.6-Gbps signal for the same 4.5 meters.
	www.commsdesign.com /main/multsupp/0002/0002fire.htm (3034 words)

	Instrutech Corporation - Precision instrumentation for Biological Research
		A unique digital PCM tape encoding technique, together with state of the art microprocessor and digital signal processing technology provides for stable low noise recordings superior to that of analog FM devices.
		Since there are sixty frames of data per second in NTSC format, this makes locating data on the tape accurate to within sixteen milliseconds.
		The VR-100B has a parallel data interface to allow for the direct transfer of data to a computer system *.
	www.instrutech.com /html/vr100lit.html (845 words)

	[No title]
		The sender writes the data to be sent into the serial data register and waits for the transfer to complete.
		Two wires are needed: one to connect the serial bus data line to the syncronous serial port data line and one to connect the serial bus SRQ (the obsolete line for service request, now fast serial clock) to the synchronous serial port clock line.
		Therefore, to decode the image data: read in the bits, find the Huffman code, unpack the RLE, de-quantize the data, and perform the inverse transform, for each 8x8 block of image data to be plotted to the screen.
	www.ffd2.com /fridge/chacking/c=hacking19.txt (10948 words)

	Atari 8-Bit Computers: Frequently Asked Questions
		The display list and the display data are written into RAM by the 6502.
		In addition to the digital track that stores computer data, a second audio track is provided to play music or voice as the program runs.
		D7 + 9 No connection to shield + Frame - to the shield wire Because the 850 was relatively expensive, provided more capabilities than the average user was looking for, and was at times unavailable from Atari despite high demand, there were many 3rd-party interfaces designed to provide some compatible subset of the 850's features.
	www.faqs.org /faqs/atari-8-bit/faq (14140 words)

	Cyberbat Update for Asteroid Mining Technology (Site not responding. Last check: 2007-10-26)
		The procedure searches the radar data stream at the input port and returns auxiliary data in the aux array and the range value in rangex (if it is an HH pulse) and radar data in the rod array.
		When the last pulse data in a frame is received, the current time value is inserted into the next position in lats.
		Therefore, data is stored in the two fifo processes between when it is generated and when it is to be presented at the output port.
	inprosys.bizland.com /website/1cyberbat.htm (3739 words)

	Instrutech Corporation - Precision instrumentation for Biological Research
		A unique digital PCM tape encoding technique, together with state of the art microprocessor and digital signal processing technology provides for stable low noise recordings.
		This greatly expands storage capacity over that of conventional computer memory storage and allows the research scientist to store all his experimental data safely for subsequent retrieval and examination.
		Since there are sixty frames of data per second in NTSC format, this makes location of a section of data on the tape accurate to within sixteen milliseconds.
	www.instrutech.com /html/vr10lit.html (921 words)

	Indigita Corporation : News
		The TSB81BA3 is a three-port bilingual physical layer device capable ofspeeds up to 800 Mbps, compliant with the approved version of the IEEE 1394bspecification.
		This first to be announced IEEE 1394b PHY not only doubles thespeed of previous generation 1394a PHYs to 800 Mbps but also increasescommunication distances up to 100 meters, ensuring a much better userexperience in high speed data transfers and multimedia networking.
		The TSB81BA3 is backward-compatible with 1394a devices, supporting boththe data strobe encoding scheme of IEEE 1394a-2000 and the new 8B/10B encodingscheme for 1394b.
	www.indigita.com /newsite/company/news/ti-1394b.html (641 words)

	strobe - OneLook Dictionary Search
		Tip: Click on the first link on a line below to go directly to a page where "strobe" is defined.
		STROBE : Technical Glossary of Theatre Terms [home, info]
		Phrases that include strobe: strobe light, column address strobe, row address strobe, address strobe, data strobe encoding, more...
	www.onelook.com /?w=strobe (186 words)

	Mike's FireWire Information (Site not responding. Last check: 2007-10-26)
		David was also the one that pushed to allow Firewire to act like a memory bus, which was the key innovation that allows Firewire disks to be their own DMA controllers..
		Paul Walker and others at ST Microelectronics invented the data-strobe encoding system used in 1394 and 1394a.
		S200 is twice the S100 rate (S100 is also called the "base rate"), S400 is 4 times the base rate, etc. These odd numbers were chosen because they are nice multiples of the data rates used by digital audio, so it allowed Apple to use one less crystal in their systems.
	www.teener.com /FireWire (1642 words)

	Wang 2200 Microarchitecture Description (Site not responding. Last check: 2007-10-26)
		Another type of strobe is "-OBS", or "Output Bus (Data) Strobe", which causes the value of the K register to be driven on the I/O bus followed by a ~5 microsecond data strobe signal.
		On a write, the vertical/horizontal addressing mode bit combines with the write 1/write 2 mode control and the PC to write one nibble of data; this nibble is selected by the src A operand for the mini-op instructions, otherwise it comes from the ALU output.
		The operations at 03C1 and 03C2 write the two nibbles, encoded as ",W1" and ",W2", represent the nibbles at MEM[PC] and MEM[PC^0x0001], that is, an adjacent nibble pair.
	www.thebattles.net /wang/uarch.html (2927 words)

	SpaceWire: The Standard
		SpaceWire is an emerging standard for high-speed data handling which is intended to meet the needs of future, high-capability, remote sensing instruments.
		SpaceWire is based on two existing commercial standards, IEEE-1355 [1] and LVDS [2, 3] which have been combined and adapted for use on-board spacecraft.
		The paper begins with an overview of the requirements for high-speed data links on-board a spacecraft.
	klabs.org /richcontent/Papers/Synopses/SpaceWire.htm (343 words)

	THE WAVE REPORT ON DIGITAL MEDIA (Site not responding. Last check: 2007-10-26)
		All processor-related peripherals of the MDE 9500 as well as the MPEG-related hardware controllers are connected to the microcontroller via a high-performance on-chip bus.
		The 1394b PHY chip is a three-port, bilingual device that is backward compatible with 1394a devices, supporting the data strobe encoding scheme of IEEE 1394a-2000, and the 8B/10B encoding scheme for 1394b.
		The device is compatible with the PCI Power Management 1.1 specification, enabling active power management by the Windows operating system, and integrated intelligent power management, which allows the device to conserve power for power-sensitive applications like portable computers and handheld devices.
	www.wave-report.com /2001_Wave_Issues/wave0139.htm (4544 words)

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