| | Active load for emitter coupled logic gate US Patent 4806796 (Site not responding. Last check: 2007-10-08) |
 | | Emitter follower transistor 37 has its emitter coupled to voltage terminal V.sub.EE by current source 38 and connected to output terminal 39, its base connected to the collector of transistor 31, and its collector coupled to voltage terminal V.sub.CC. |
 | | Emitter follower transistor 37' has its emitter coupled to voltage terminal VEE by current source 38' and connected to output terminal 39', its base connected to the collector of transistor 30, and its collector coupled to voltage terminal V.sub.CC. |
 | | Emitter follower transistor 47 has its emitter coupled to voltage terminal V.sub.EE by current source 48 and connected to output terminal 49, its base connected to the collector of transistor 41, and its collector coupled to voltage terminal V.sub.CC. |
| patents.nimblewisdom.com /patent/4806796-Active-load-for-emitter-coupled-logic-gate (2748 words) |