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Topic: Execution units

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	Hybrid execution unit for complex microprocessor - Patent 5574942
		The hybrid execution unit of claim 1 wherein said control block in response to said single cycle instruction generates control signals to drive said data path to generate result data comprising a predetermined portion of said first source operand concatenated with a predetermined portion of said second source operand.
		The hybrid execution unit includes the necessary control logic for directing the data path to perform the various data manipulations or swizzling that are described with respect to the implemented instructions.
		The control logic of the hybrid execution unit would then have to decode the incoming opcode which is provided to all the execution units and write the necessary information on the correct bits of the output busses simultaneously with the other execution unit writing back the result data on the remaining output bus bits.
	www.freepatentsonline.com /5574942.html (9044 words)

	FM 90-7 Chapter 6. Reserve Obstacles
		Units execute them only on command of the authorizing commander or based on specific criteria that the commander identifies.
		Units normally install, but do not execute, reserve obstacles early in the preparation phase because they are a critical part of the plan.
		If execution is based on a certain size enemy force reaching the obstacle site, the guard commander uses the time required for obstacle execution and works backwards to locate the DP to execute the obstacle.
	www.globalsecurity.org /military/library/policy/army/fm/90-7/f907_7.htm (2442 words)

	History of the PowerPC Architecture
		Decode/Source: In dispatch, the dispatch unit reads the bottom two entries of the instruction queue (or alternately the special branch resolution queue), then reads available source operands, and finally allocates renaming registers and sends instructions to the corresponding execution units.
		If a CR bit is unavailable, the branch unit predicts either branch taken or branch not taken paths depending on the bits in the branch opcode.
		The load/store unit is fully pipelined, so the load can be dispatched at the rate of one per clock cycle, but since the store needs to check for memory protection violation, stores cannot be executed in a fully pipelined manner.
	www.cs.pitt.edu /~alanjawi/p603.html (1448 words)

	History of the PowerPC Architecture
		Unlike the other execution units, the load-store unit does not deallocate a reservation station entry as soon as an instruction is issued.
		For each execution unit, the overall execution latency is the actual execution time of an instruction plus the waiting time in the reservation stations.
		Even with the precise interrupts support, the out-of-order execution in the 620 is still able to achieve a reasonable degree of instruction-level parallelism, with average IPC of 1.23 for integer benchmarks and 1.26 for floating-point benchmarks.
	www.cs.pitt.edu /~alanjawi/p620.html (1130 words)

	The Microarchitecture of the Pentium® 4 Processor
		These schedulers determine when uops are ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resources the uops need to complete their operation.
		The execution units are designed to optimize overall performance by handling the most common cases as fast as possible.
		The Pentium 4 processor execution units are designed to optimize overall performance by handling the most common cases as fast as possible.
	developer.intel.com /technology/itj/q12001/articles/art_2e.htm (4953 words)

	CmpSci 635 Lecture 8
		For example, if execution averages several cycles, and the number of functional units is small, then a single pipe may be able to keep the units utilized.
		A completion unit ensures that the register file is updated in a manner that is consistent with sequential semantics under an exception (actually, a parity error can result in imprecise state, but because it isn't recoverable, it doesn't matter).
		Each of the execution units has a two-entry reservation station that enables instructions to be issued before their operands are available.
	www.cs.umass.edu /~weems/CmpSci635/635lecture8.html (3581 words)

	POWER4 System Microarchitecture -- Page 3
		To guard against this, as a store instruction executes it checks the LRQ and if it finds a younger load that has executed and loaded from memory locations the store is writing to, the group containing the load instruction and all younger groups are flushed and refetched from the instruction cache.
		During the ISS cycle the IOP is issued to the appropriate execution unit, reads the appropriate register to retrieve its sources during the RF cycle and executes during the EX cycle writing its result back to the appropriate register during the WB cycle.
		Though not shown, the CR Logical Execution Unit, the unit responsible for executing logical operations on the Condition Register, is identical to the Fixed Point Execution pipeline, shown as the FX pipeline in the figure.
	www.ibm.com /servers/eserver/pseries/hardware/whitepapers/power4_3.html (2300 words)

	Port swapping for improved virtual SRAM performance and processing of concurrent processor access requests - Patent ...
		Although providing separate caches to each execution would eliminate this problem, this solution increases system cost by requiring the addition of another cache array, This also results in added system complexity and redundancy, in that each execution unit is no longer sharing a common cache or executing a common instruction/data stream.
		In order to improve cache performance the order in which the cache executes accesses is determined by the type of access such that when a wrtie access is received on one port and a read access on a second port, the read access is executed first in order to improve the performance of the cache.
		There is no conflict between execution unit access and cache reload since the former occurs during the first portion of the clock cycle, whereas the latter occurs during the second portion of the clock cycle.
	www.freepatentsonline.com /5561781.html (4437 words)

	[No title]
		Increasing the width of the execution core definitely has its advantages, but there's a limit to how wide the core can be before you reach a point of diminishing returns.
		The more execution units the processor's execution core has, the larger the instruction window needs to be in order to extract even more parallelism from the code stream.
		These idle execution units are still taking up die space and drawing power, so widening a processor is therefore a relatively inefficient way to increase its performance.
	arstechnica.com /articles/paedia/cpu/xbox360-2.ars (718 words)

	POWER3: The next generation of PowerPC processors
		The single-cycle units execute all single-cycle instructions (arithmetic, shift, logical, compare, trap, and count leading zero) with a single-cycle latency (this means that instructions dependent upon the result can execute in the next cycle).
		The independence of the fixed-point execution units and the load/store execution units is obviously a large performance benefit for calculations that are predominately integer in nature, such as Monte Carlo simulations.
		In the case of data forwarding between execution units, or when, on the same execution unit, the first instruction is feeding the FRA operand of the dependent instruction, the latency is four cycles.
	www.research.ibm.com /journal/rd/446/oconnell.html (7426 words)

	postrisc2
		For example, the execution units of these processors are optimized to complete most instructions in a single cycle.
		To allow the instruction fetch unit to fetch the next instruction without waiting for decode phase and branch lookup, flow history bits are added to each group of four instructions.
		After the execution units have executed the instructions from the queue, the results are retired in order enforcing the expected sequential nature of the program, hiding the dataflow nature of the processor core.
	www.cse.msu.edu /~enbody/postrisc/postrisc2.htm (4908 words)

	week 9 notes [multiple execution units, vliw vs. superscalar, caches]
		when we introduce multiple execution units into our pipeline, we end up with a strange looking pipeline that includes several "sub-pipelines" for execution.
		the examples in lecture have one execution stage for integer operations, seven execution stages for fp multiplies, and four execution stages for fp additions.
		when we have a pipeline with multiple execution units, a number of problems appear that we didn't have to deal with before: structural hazards, and write-after-write dependencies.
	www-cse.ucsd.edu /~j2lau/cs141/week9.html (1507 words)

	AltiVec Performance Issues
		In this phase an instruction is moved from one of the dispatch buffers to the portal of the appropriate execution unit.
		In front of each execution unit on a 970, there is a queue where dispatched instructions reside until the data that they need becomes available so that they can execute.
		In this phase the instruction is actually executed by the execution unit to which it was dispatched.
	developer.apple.com /hardware/ve/performance.html (2768 words)

	Replay system - Wikipedia, the free encyclopedia
		Its primary function is to catch operations that have been mistakenly sent for execution by the processor's scheduler.
		Because of this, there are 6 stages between the scheduler and the execution units in the Prescott core.
		Under normal circumstances, the execution units in the Pentium 4 are in use roughly 33% of the time.
	en.wikipedia.org /wiki/Replay_system (411 words)

	Execution unit Summary
		Some of the functional units within a CPU that enable it to perform its functions are: (1) The arithmetic-logic unit (ALU) performs arithmetic and logic functions (operations) on binary numbers (0 and 1).
		In computer engineering, an execution unit is a part of a CPU that performs the operations and calculations called for by the program.
		It may have its own internal control sequence unit (not to be confused with the CPUs main control unit), some registers, and other internal units such as a sub-ALU or FPU, or some smaller, more specific components.
	www.bookrags.com /Execution_unit (844 words)

	Inside Intel Core Microarchitecture \| Hardware Secrets
		Pentium 4 and Pentium M have a separated address generation unit, and on Pentium 4 the first ALU is used to store data on memory.
		Load: Unit to process instructions that ask a data to be read from the RAM memory.
		While this unit is processing a very complex instruction that takes several clock ticks to be executed, port 2 won’t stall: it will keep sending simple instructions to the IEU while the FPU is busy.
	www.hardwaresecrets.com /printpage/313/4 (616 words)

	XMIM v4x Lesson 9 (Site not responding. Last check: 2007-11-03)
		Execution Units to some time less than daily.
		Execution Units window, change the “1 Day” default to “15 Minutes”.
		Time Offset menu selection is used to pick a date, relative to 'today' or the current date or time executed within the system.
	www.lim.com /doc/xmim101e_exceed/lesson9.htm (1679 words)

	[No title]
		Static execution is simple to implement and takes up much less die space than dynamic execution, since the processor doesn't need to spend a lot of transistors on the instruction window and related hardware.
		The end result is that the when running a multithreaded workload, the Xbox 360's three-core processor will contain a higher total number of execution units that are busy at any given moment than a comparable single-core processor.
		Each individual thread has a limited amount of ILP and each PPE has a very narrow execution core, but the combined effect of a large number of simultaneously running threads means that more total execution units are put to work at once across all three PPEs.
	arstechnica.com /articles/paedia/cpu/xbox360-2.ars/2 (643 words)

	Chinese courts purchasing mobile execution units : AZ IMC
		In March, the magazine Beijing Today reported that the special vans were equipped with technology to carry out executions by lethal injection, a marked difference from China's traditional method of firing a bullet into the back of the head.
		China is the world's leading country employing capital punishment, but the number of death sentences and executions are closely guarded state secrets.
		Unless otherwise stated by the author, all content is free for non-commercial reuse, reprint, and rebroadcast, on the net and elsewhere.
	arizona.indymedia.org /mail.php?id=14290 (360 words)

	LabVIEW and Hyperthreading- Developer Zone - National Instruments
		Therefore, any application that is limited by floating-point execution units performs better on the multiprocessor computer because you do not have to share the execution units.
		When the operating system finishes executing, it stores additional clumps that meet the input conditions on the run queue, which allows the block diagram to execute in any of the available four execution threads.
		In some situations, two threads execute simultaneously on different logical processors, and one thread needs to read from the debug information at the same time that another thread is writing to the debug information.
	zone.ni.com /devzone/cda/tut/p/id/3558 (3141 words)

	BYTE.com
		The PA-8000's instruction-fetch unit fetches blocks of four quadword-aligned instructions per cycle (exactly matching the maximum execution rate) from the external I-cache.
		This enables the PA-8000 to execute (but not retire) many instructions speculatively, without corrupting the processor state if the speculation proves false and all of them have to be scrapped.
		It executes instructions from the predicted arm of every conditional branch but doesn't retire them until the branch condition is resolved.
	www.byte.com /art/9507/sec11/art1.htm (1710 words)

	VMX Units on the X360 CPU - Beyond3D Forum (Site not responding. Last check: 2007-11-03)
		A multithreaded processor can't execute more operations/cycle than a single-threaded processor with the same number of execution units no matter how many hardware threads are implemented in it; one, two, even more.
		Is the VMX unit separate from the other execution units or does it block the execution of parallel threads.
		If the execution units were doubled, it wouldn't be a three-core chip, but a six-core chip.
	www.beyond3d.com /forum/showthread.php?t=20277 (2286 words)

	THE VLIW COMPILER (Site not responding. Last check: 2007-11-03)
		In VLIW architecture, the relationship between the position of the instructions to be issued and the execution unit is strictly defined, and the compiler must constantly be aware of this relationship.
		Multiple execution units may be connected to one slot, or at mode switching the execution unit may become disconnected from a slot.
		The compiler should also be able to recognize areas in the program that can be executed in parallel as failure to do this will increase the number of no-ops (no operations) thereby reducing the speed advantage of VLIW processors over uniprocessors like RISC and CISC.
	www.wam.umd.edu /~nbatra/411proj/vliwcompiler.htm (761 words)

	Instruction Format
		Four execution units are available for each instruction.
		The 5-bit template allows for the theoretical encoding of 32 cases of parallel/serial execution on a combination of execution units, but currently only 24 are defined.
		Interestingly, all bundles must be organized to execute in parallel with the exception of I-Unit and M-Unit combinations (an I-Unit execution followed by and I-Unit and an M-Unit, or an M-Unit followed by and I-Unit and an M-Unit).
	www.cs.nmsu.edu /~rvinyard/itanium/instruction_format.htm (119 words)

	Dual cache for independent prefetch and execution units (US4701844)
		When the ALPU performs a write operation to main memory, it also updates the corresponding data in the operand cache and, if contained therein, in the instruction cache permitting the use of self-modifying code.
		means enabling said arithmetic logic processing unit to write information simultaneously into said main memory unit and into said instruction cache memory unit in response to said first signal; and
		means enabling said arithmetic logic processing unit to write information simultaneously into said main memory and into said operand cache memory unit in response to said second signal.
	www.delphion.com /details?patent_number=4701844 (400 words)

	X-bit labs - Articles - Prescott: The Last of the Mohicans? (Pentium 4: from Willamette to Prescott). Part II (page 5)
		So, the primary goal of the pipeline managing logics is to load the processor execution units to their maximum capacity.
		This time interval is determined by the time the first operation requires for execution (to be more exact, for the result of this execution to be ready for further processing).
		By the time the first micro-operation is about to be executed, the next micro-operations are already coming close taking different pipeline stages, and the scheduler is busy working on the next micro-operation already.
	www.xbitlabs.com /articles/cpu/display/netburst-2_5.html (639 words)

	[No title] (Site not responding. Last check: 2007-11-03)
		An execution unit is the center of the processor.
		An execution unit has instructions and data as its inputs and it executes the instruction on the data.
		Having multiple execution units allows the core to process multiple instructions in parallel, thus theoretically increasing performance by a factor equal to the number of execution units.
	www.louisville.edu /~ljditr01/CellProcessor.doc (4264 words)

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