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	Explicitly Parallel Instruction Computing - Wikipedia, the free encyclopedia
		Explicitly Parallel Instruction Computing ('EPIC) is a computing paradigm that began to be researched in the 1990s.
		One goal is to move the complexity of dynamic scheduling of multiple instruction issue from the hardware implementation to the compiler, which can do the instruction scheduling statically (with help of trace feedback information).
		predicated execution is used to decrease the occurrences of branches and increase the speculative execution of instructions.
	en.wikipedia.org /wiki/Explicitly_Parallel_Instruction_Computing (563 words)

	VLIW: old architecture of the new generation
		Moreover, the EPIC improves the ability of the compiler to generate plans of execution statically at the expense of various code transitions during compilation which are not correct in the serial architecture.
		EPIC was developed exactly to reach a higher degree of parallel instruction computing with an acceptable hardware complexity.
		All such instructions can be divided into instructions of operation with a register stack, integer instructions, instructions of comparison and operation with predicates, memory access instructions, jump instructions, multimedia instructions, interregister move instructions, "miscellaneous" instructions (operations with lines and count of bits in a word) and floating-point instructions.
	www.digit-life.com /articles2/vliw (6438 words)

	Instruction level parallelism - Wikipedia, the free encyclopedia
		Instruction-level parallelism (ILP) is a measure of how many of the operations in a computer program can be performed simultaneously.
		If we assume that each operation can be completed in one unit of time then these three instructions can be completed in a total of two units of time, giving an ILP of 3/2.
		Instead, the industry is heading towards exploiting higher levels of parallelism that is available through techniques such as multiprocessing and multithreading.
	en.wikipedia.org /wiki/Instruction_level_parallelism (296 words)

	HP and Intel Unveil Breakthrough EPIC Technology at Microprocessor Forum (Site not responding. Last check: 2007-10-17)
		EPIC, incorporating an innovative and unique combination of speculation, predication and explicit parallelism, is expected to advance the state of the art in processor technologies, specifically addressing the performance limitations found in today's RISC (Reduced Instruction Set Computing) and CISC (Complex Instruction Set Computing) technologies.
		EPIC technology breaks through the sequential nature of today's conventional processor architectures by allowing the software to communicate explicitly to the processor when operations can be done in parallel.
		It is the second-largest computer supplier in the United States, with computer-related revenue in excess of $31.4 billion in its 1996 fiscal year.
	www.intel.com /pressroom/archive/releases/SP101497.HTM (685 words)

	Explicitly Parallel Instruction Computing (EPIC) instruction set (Site not responding. Last check: 2007-10-17)
		An Instruction Group is a set of instructions with no data dependencies which can execute in parallel.
		Instruction groups are composed of instructions in bundles.
		Compiler will decide which instructions can be executed in parallel.
	pages.cpsc.ucalgary.ca /~ijirasek/courses/cpsc401/epic_instr.htm (192 words)

	IA-64: Definition and Links by Encyclopedian.com - All about IA-64
		In an EPIC design the instructions that have no dependencies and can be executed in parallel are segregated (based on a predefined set of templates) into Instruction Groups and fed into the processor as manageable chunks.
		Thus we have explicit instructions for multimedia operations, and explicit instructions for floating point operations.
		Above all when a 32-bit instruction (32-bit application) is run on a 64-bit machine the processor temporarily switches to 32-bit mode and returns to 64-bit mode on completion.
	www.encyclopedian.com /ia/IA64.html (359 words)

	A 64-bit Instruction Set Architecture (ISA) Based on EPIC Technology
		Branches (instructions that change the flow of execution within the program) and memory latency (the time for data to arrive from memory) compound the already limited ability of today’s processors to achieve parallel execution.
		Intel and Hewlett-Packard jointly defined a new architecture technology called EPIC (Explicitly Parallel Instruction Computing) named for the ability of the software to extract maximum parallelism (potential to do work in parallel) in the original code and "explicitly" describe it to the hardware.
		One of the key objectives for the new instruction set architecture was to enable a wide range of implementations to balance different performance and cost requirements.
	www.cpushack.net /CIC/otherpr/epic-info.html (1360 words)

	DRACO (Site not responding. Last check: 2007-10-17)
		Parallelism has been the primary architectural mechanism to increase computer system performance.
		To continue pushing the performance envelope, identifying new sources of parallelism for future architectures is critical.
		From this perspective, the Explicitly Parallel Instruction Computing (EPIC) ISA is an interesting model for future machines as its primary design allows software to expose analysis information to the underlying processor for it to exploit parallelism.
	rogue.colorado.edu /draco/abstract.php?pub=epic05-ilp.pub&paper_dir=papers (234 words)

	Incorporating Predicate Information Into Branch Predictors
		The Explicitly Parallel Instruction Computing (EPIC) architecture has been put forth as a viable architecture for achieving the instruction level parallelism (ILP) needed to keep increasing future processor performance.
		One of the new features of the EPIC architecture is support for predicated execution, where each operation is guarded by one of the predicate registers available in the architecture.
		As this type of EPIC architecture progresses and memory latencies are better hidden, the stalls due to branch mispredictions will have a much larger impact.
	www-cse.ucsd.edu /users/calder/abstracts/EPIC-01-PBP.html (794 words)

	EPIC-2 Workshop (Site not responding. Last check: 2007-10-17)
		The Explicitly Parallel Instruction Computing (EPIC) architecture model has the potential of achieving unparalleled levels of performance in future computer systems.
		The EPIC style of architecture was developed to enable higher levels of instruction-level parallelism.
		The major challenge to realizing the full potential of EPIC architectures is developing strategic compiler technologies that effectively deploy explicitly defined hardware mechanisms and deliver performance for both commercial and scientific applications.
	systems.cs.colorado.edu /EPIC2/cfp.html (256 words)

	Why Itanium for technical computing - architecture benefits (Site not responding. Last check: 2007-10-17)
		Explicit Parallel Instruction Computing (EPIC) lies at the heart of Itanium.
		EPIC allows Itanium to split application code into multiple streams and run each stream simultaneously, accelerating throughput and optimizing use of resources.
		Then, when you are ready, you can finish transitioning your applications to 64-bit Itanium computing to achieve optimal performance from this novel and powerful processor family.
	www.hp.com /products1/itanium/solutions/technical_computing/arch_benefits (450 words)

	Computing Canada: A Technology Of EPIC Proportions : Manufacturer says it gives the Itanium processor a higher ... (Site not responding. Last check: 2007-10-17)
		Computing Canada: A Technology Of EPIC Proportions : Manufacturer says it gives the Itanium processor a higher instruction level parallelism than was previously available - Explicitly Parallel Instruction Computing
		It's been called the biggest innovation in high-end computing since RISC (Reduced Instruction Set Computing) appeared on the scene in the 1980s.
		Key to its operation is EPIC (Explicitly Parallel Instruction Computing), a technology that Intel says gives the processor a higher instruction level parallelism than was previously available, up to 20 operations simultaneously, enabling better performance for targeted applications.
	www.findarticles.com /p/articles/mi_m0CGC/is_20_27/ai_78573978 (718 words)

	USENIX '05 — Technical Paper, General Track
		EPIC is based on the realisation that the ILP that can be usefully exploited by reordering is limited, and aims at raising this limit.
		Each clock cycle, all instructions in the issue window are dispersed into back-end pipelines (branch, memory, integer and floating-point) as directed by the template, unless a required pipeline is stalled or a stop is encountered in the instruction stream.
		The EPIC approach has proven a formidable challenge to compiler writers, and almost five years after the architecture was first introduced, the quality of code produced by the available compilers is often very poor for systems code.
	www.usenix.org /events/usenix05/tech/general/gray/gray_html (8892 words)

	Ingenuity Introduction - 10/98 - ECE group plays key role in Trimaran advanced compiler research infrastructure
		HP and Intel are developing EPIC technology for use in the IA-64 (Merced) processor due in mid-2000.
		EPIC, the foundation of the 64-bit Instruction Set Architecture (ISA), uses predication, speculation, explicit parallelism and other qualities to deliver superior processing performance and inherent scalability not available with conventional RISC architectures.
		EPIC compilers use access to architectural information and control over processor execution to expose, exploit, and orchestrate opportunities for parallelism within an application, thus extracting maximum speed and performance from EPIC/IA-64 systems.
	www.ece.uiuc.edu /ingenuity/1098/trimaran.html (619 words)

	InformationWeek > Itanium 2 > Days Before Launch, Intel Defends Right To Use Itanium 2 Technology > July 3, ... (Site not responding. Last check: 2007-10-17)
		EPIC lets the chip receive data in parallel streams instead of processing it linearly.
		Intergraph claims it invented the type of parallel computing used by Itanium in 1992.
		At the time, the company was still in the processor-design business and developed and patented a technology called PIC, or parallel instruction computing.
	www.informationweek.com /story/IWK20020703S0013 (623 words)

	IA-64 Processor - Digital Engineering Institute (Site not responding. Last check: 2007-10-17)
		The first implementation of the IA-64 architecture achieves high performance by using a highly parallel execution core, while maintaining binary compatibility with the IA-32 instruction set.
		Explicitly parallel instruction computing (EPIC) design maximizes performance through hardware and software synergy.
		Clock deskew, design for test, explicitly parallel instruction computing, IA-64, I/O compensation, microprocessor, source-synchronous bus.
	www.klabs.org /DEI/Processor/IA-64 (288 words)

	HP and Intel to release open IA-64 Instruction Set Archutecture (Site not responding. Last check: 2007-10-17)
		In October 1997, Intel and HP announced that the IA-64 architecture would utilize a new technology called EPIC (Explicitly Parallel Instruction Computing), based on a combination of advanced computer architecture concepts called speculation, predication and explicit parallelism.
		Instructions will be bundled in groups for parallel execution by the various functional units.
		The instruction set has been optimized to address the needs of cryptography, video encoding and other functions that will be increasingly needed by the next generation of servers and workstations.
	www.hoise.com /primeur/99/articles/monthly/SW-PR-07-99-10.html (335 words)

	[No title] (Site not responding. Last check: 2007-10-17)
		ELI stands for Enormously Longword Instructions; 512 is the size of the instruction word we hope to achieve.
		A serious concern with this class of processors, due to their very long instructions, is their code size.
		In fact, another instruction set trend has been the introduction of instructions geared toward subword operations on 16-bit quantities.
	www.tug.org /ftp/pub/tex/bib/intel-ia-64.bib (842 words)

	Hewlett-Packard Labs Worldwide-News- EPIC (Explicitly Parallel Instruction Computing)
		The infrastructure is expected to facilitate instruction and research in EPIC technology and to lower the barrier to entry for research and instruction in this field greatly.
		The research infrastructure produced through these cooperative efforts is available free of charge at http://www.trimaran.org to universities interested in studying EPIC compilers.
		EPIC, the foundation of the 64-bit Instruction Set Architecture (ISA), uses predication, speculation, explicit parallelism, and other qualities specific to EPIC technology to deliver superior processing performance and inherent scalability not available with conventional RISC architectures.
	www.hpl.hp.com /news/news_archives/epic.html (495 words)

	EETimes.com
		Explicitly Parallel Instruction Computing (EPIC) was the marketing term Intel coined for the concept.
		The EPIC idea rests on a number of familiar ideas, all of which will be new to the Intel world.
		The expression determines whether the instruction results are retired to the register file or ignored when the instruction is completed.
	www.eetimes.com /news/97/976news/details.html (484 words)

	DSS- Direct Systems Support. For state-of-the-art IBM solutions (Site not responding. Last check: 2007-10-17)
		The Intel® Itanium processor is the first in a family of processors based on the new Itanium architecture.
		The powerful new processor family extends open-standards-based computing to the enterprise, delivering flexibility, choice and value over proprietary solutions.
		Its Explicitly Parallel Instruction Computing (EPIC) technology allows the processor to execute multiple instructions simultaneously and includes features that overcome legacy performance limitations.
	www.directsystemssupport.com /cgi-bin/db2www/company/press/10702.d2w/report (245 words)

	64 bit-celsius v-fujitsu siemens-amd-intel-pci x-pci 3-sas-scsi-nvidia-3dlabs
		We live in a world where computers built to play games can cost more and run faster than the computers used to create those games.
		Professional computer users rarely have the budget to operate on the bleeding edge of computer technology, and some of gamers' techniques, such as overclocking, are inappropriate for a commercial environment.
		EPIC was created to allow the processor to run more instructions at once than conventional CPUs.
	bg.millimeter.com /ar/video_finding_gamers_edge (2087 words)

	CNETAsia : Printer Friendly - Intergraph: Intel Itanium violates patent (Site not responding. Last check: 2007-10-17)
		Itanium, based on the IA-64 platform developed by Intel and Hewlett-Packard, was officially launched earlier this year after delays and testing.
		It uses the EPIC (explicitly parallel instruction computing) instruction set, which the lawsuit claims conflicts with 1993 Intergraph patents relating to instruction routing and parallelism.
		The patents cover parallel instruction computing (PIC) techniques used to convey parallelism to hardware and a method of routing instructions to processing units, according to Intergraph.
	asia.cnet.com /news/systems/printfriendly.htm?AT=20099071-39037054t-39000006c (298 words)

	EPIC - a Whatis.com definition - see also: Explicitly Parallel Instruction Computing
		EPIC (Explicitly Parallel Instruction Computing) is a 64-bit microprocessor instruction set, jointly defined and designed by
		By comparison, current 32-bit CISC and RISC microprocessor architectures depend on 32-bit registers, branch prediction, memory latency, and implicit parallelism, which are considered a less efficient approach in microarchitecture design.
		IA-64 (Intel Architecture-64), Intel's first 64-bit CPU microarchitecture, is based on EPIC.
	searchcio.techtarget.com /sDefinition/0,,sid19_gci214560,00.html (210 words)

	Computing Canada: EPIC performance on the processor horizon - HP and Intel detail new 64-bit Explicitly Parallel ... (Site not responding. Last check: 2007-10-17)
		Computing Canada: EPIC performance on the processor horizon - HP and Intel detail new 64-bit Explicitly Parallel Instruction Computing processor architecture - Company Business and Marketing - Brief Article
		Hewlett-Packard Co. and Intel Corp. have released the technical concepts of their jointly defined foundation for the new 64-bit Instruction Set Architecture (ISA) known as EPIC (Explicitly Parallel Instruction Computing).
		According to the companies, EPIC "breaks through the sequential nature of today's conventional processor architectures by allowing the software to communicate explicitly to the processor when operations can be done in parallel.
	www.findarticles.com /p/articles/mi_m0CGC/is_n24_v23/ai_20069332 (266 words)

	Abstract (Site not responding. Last check: 2007-10-17)
		This talk outlines the key architectural advances included in the 64-bit instruction set jointly defined by Intel and HP in a joint research activity that started in June of 1994.
		The set of techniques is named EPIC, for Explicitly Parallel Instruction Computing.
		This talk briefly covers the history and motivation for EPIC, the key elements of EPIC, some code examples illustrating the benefit of the EPIC techniques, and a sketch of how the EPIC technology processors fit into Intel's microprocessor roadmap.
	www.cs.cmu.edu /~tcm/cs_seminars/crawford_abstract_s98.html (256 words)

	Beyond Proprietary Computing, from Intel - White Papers, Webcasts, and Case Studies - ITPapers
		By adopting an open, multi-vendor computing model rather than a closed, proprietary strategy, businesses can realize new levels of scalability, reliability, manageability, performance, and cost-effectiveness.
		This new approach to enterprise computing, one that employs pervasive and flexible solutions to deliver advanced capabilities, is called macroprocessing.
		The Intel® Itanium® processor family employs 64-bit memory addressibility and Explicitly Parallel Instruction Computing (EPIC) to perform as many as 20 operations simultaneously, making it a perfect fit for back-end servers in the most demanding, enterprise-class environments.
	www.itpapers.com /abstract.aspx?kw=epic&docid=33294 (348 words)

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