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Topic: FIFO

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	EDN Access--03.14.97 FIFO memories supply the glue for high-speed systems
		The disadvantage of a strobed FIFO device is that it cannot fully synchronize the status signals with the corresponding clock signals.
		Clocked FIFOs are similar, except that during writes or reads the system sometimes (depending on the device) asserts the chip select, and the input (output) flag is multistage synchronized to the write (read) clock.
		This scheme ensures that the upstream FIFO device does not attempt to force another data word upon the downstream FIFO device when the downstream device is full and vice versa for reads when the device is empty.
	www.edn.com /archives/1997/031497/06DF_02.htm (2198 words)

	FIFO (Site not responding. Last check: 2007-11-01)
		In electronics a FIFO is a semiconductor memory in which first data to be written is always first data to be read.
		A FIFO with a clock input called a synchronous FIFO; otherwise it is The device typically has outputs called flags indicate when it is empty or full.
		In accounting FIFO is a common method for approximating value of inventory.
	www.freeglossary.com /FIFO (337 words)

	FIFO - Wikipedia, the free encyclopedia
		FIFOs are used commonly in electronic circuits for buffering and flow control.
		For FIFOs of non-trivial size a dual-port SRAM is usually used where one port is used for writing and the other is used for reading.
		In the hardware FIFO is used for synchronization purpose.
	en.wikipedia.org /wiki/FIFO (529 words)

	FIFO Frame Grabbers (Site not responding. Last check: 2007-11-01)
		The important property of the FIFO buffer is that it does not need to be completely emptied before the new data could be written into it.
		With the FIFO frame grabber the image is being transferred as it is digitized, with the only delay being a FIFO delay (a few microseconds).
		To be objective we have to mention that with the FIFO frame grabbers there is a remote possibility of loosing data in case of extreme PCI latencies.
	www.sensoray.com /html/fifo.html (747 words)

	fifo (Linux Reviews)
		A FIFO special file (a named pipe) is similar to a pipe, except that it is accessed as part of the file system.
		Thus, the FIFO special file has no contents on the file system, the file system entry merely serves as a reference point so that processes can access the pipe using a name in the file system.
		FIFO special files can be created by mkfifo(3), and are specially indicated in ls -l.
	linuxreviews.org /man/fifo/index.html.en (333 words)

	fifo
		A FIFO special file (a named pipe) is similar to a pipe, except that it is accessed as part of the file system.
		Thus, the FIFO special file has no contents on the file system, the file system entry merely serves as a reference point so that processes can access the pipe using a name in the file system.
		FIFO special files can be created by mkfifo(3), and are specially indicated in ls -l.
	www.ctssn.com /man/index.cgi?section=4&topic=fifo (308 words)

	Daytronic Corporation - System 10 - FIFO Buffer Memory Card
		With battery-backed RAM, the FIFO buffer card is ideal for applications where it's impractical to connect a computer, printer, recorder, or other receiver directly to the mainframe while data is being acquire—as, for example, in "on-the-road" vehicle performance testing, using a DC-powered mainframe.
		FIFO setup parameters are written to EEPROM, as enabled by the "software" setting of a special system logic bit.
		s—specific commands for reaccessing the FIFO memory (should the 10AFIFO card be removed from the mainframe); for "true erasure" of memory contents, using a physical overwrite technique; and for allowing System 10 interrogation responses to temporarily bypass the FIFO memory.
	www.daytronic.com /products/10K/10AFIFO.htm (1005 words)

	ModemHelp.Net FAQs - What is a FIFO buffer? How does it work?
		FIFO stands for "First In/First Out" and is a way for the UART to process data more smoothly.
		The UART stores incoming data in the FIFO buffer, and the FIFO buffer holds it until the CPU is ready for it.
		FIFO buffers can be adjusted for the number of bytes they can hold at a time.
	www.modemhelp.net /faqs/fifo.shtml (241 words)

	[No title]
		Initializes a fifo location to represent an empty sequence of data and returns zero, or returns non-zero on failure.
		Destroys a fifo representation, releasing any resources used to represent the data sequence (abandoning any data in the queue).
		It is an error to destroy a fifo that is not initialized.
	www.globus.org /api/common/globus_fifo.html (415 words)

	Homebrew Nintendo DS Development Part 7 - FIFO
		Although the FIFO can be polled to see if items exist, it also allows interrupts to be performed when things are placed on or removed from the queue.
		The only documentation I've come across on the FIFO is from reading the DSLinux sources and DSTek.
		One good thing about using the FIFO for this sort of thing in the future is we won't need to play around with shared memory offsets to do this sort of thing.
	www.double.co.nz /nintendo_ds/nds_develop7.html (2492 words)

	FIFO status indicator - Patent 6289065
		The FIFO is a holding station for the data while en route from computer B to computer A. The FIFO may be viewed as a pipeline.
		It is a further object of the invention to provide a system which monitors the status of a FIFO buffer used in data transfer, and produces full- and empty signals in accordance with the status of the FIFO.
		In one form of the invention, a FIFO is used as a buffer to hold data while en route from a sender to a receiver.
	www.freepatentsonline.com /6289065.html (6305 words)

	POSIX FIFO and Shared Memory - fsmlabs.com (Site not responding. Last check: 2007-11-01)
		A common method for waiting for a FIFO to have data ready for read or write under UNIX is using select().
		The handler is called directly in response to the corresponding read() or write() operation and is called in the same context of those operations (including the active stack).
		There may be several file descriptors that refer to a single FIFO but they all share a single SIGPOLL handler.
	www.fsmlabs.com /posix-fifo-and-shared-memory-7.html (556 words)

	OpenSS7: Documentation: Man Pages: Manpage of CCI-BICC
		This is because a FIFO as already mounted at the point that the character or FIFO special file appears within a filesystem.
		FIFOs opened with the O_NONBLOCK flag set, for read-only, O_RDONLY, operation, when no process has the FIFO open for writing will not block, will succeed and return zero to the call to open(2s).
		FIFOs that have no modules pushed, even when full and blocked on write, will not block on close as described under I_SETCLTIME(7), because there is no driver write queue.
	www.openss7.org /man/man2html?4+fifo (1683 words)

	LIFO FIFO
		The FIFO method is also chosen because it is easier for firms with fluctuating production cost to determine their cost of goods sold and to price their products.
		However, since FIFO does produce a higher reported income, a firm is required to pay taxes on a higher dollar amount.
		As this paper had demonstrated FIFO has certain advantages when it comes to reporting inventory value on the balance sheet; while LIFO clearly takes the advantage when cost of goods sold is calculated.
	www.student.ipfw.edu /~hassce01/lifofifo.htm (1565 words)

	IBM Software - Transaction Processing Facility (TPF) - Newsletter
		Named pipes are typically referred to as FIFOs, or FIFO special files, because data is passed in a first-in-first-out format.
		As with pipes, writing to a FIFO appends the data, and reading from it returns the data that is at the beginning of the FIFO.
		One thing to be aware of is that the open of a FIFO is by default blocking; that is, a process opening a FIFO for reading is suspended until another process has opened the FIFO for writing.
	www-306.ibm.com /software/htp/tpf/news/nv9n1/v9n1a06.htm (1473 words)

	Calculating FIFO Depth
		Fifo is used as buffering element or queueing element in the system, which is by common sense is required only when you slow at reading than the write operation.
		So size of the FIFO basically implies the amount of data required to buffer, which depends upon data rate at which data is written and the data rate at which data is read.
		So to obtain safer FIFO size we need to consider the worst case scenario for the data transfer across the FIFO under consideration.
	www.asic-world.com /tidbits/fifo_depth.html (471 words)

	First in First Out Queue by Valvano
		The advantage of using a FIFO structure for a data flow problem is that we can decouple the source and sink processes.
		A FIFO is also used when you ask the computer to print a file.
		The advantage of the FIFO is it allows you to continue to use your computer while the printing occurs in the background.
	www.ece.utexas.edu /~valvano/assmbly/fifo.htm (754 words)

	Eastern Europe and CIS Review FiFo Ost (Site not responding. Last check: 2007-11-01)
		The aim of the FiFo Ost is to support enterprises interested in the exchange with the former Soviet Union and Central Eastern and Eastern European countries as well as to convey information of each of these countries.
		FiFo Ost offers a service to enterprises, institutions, entrepreneurs and others interested professionals on the requirements for proposed business ventures in Eastern Europe within the economic, legal and political framework.
		FiFo Ost publishes articles in all specialist fields that are involved with law and the economy in the eastern european countries.
	www.fifoost.org /en/fifoost/index.php (398 words)

	Verilog reg_fifo and fwft_fifo modules: Improving timing for FIFO and making a FWFT by adding registers (Xilinx and ...
		Physical distance between the FIFO and its data sink: On large devices, the data source and data sink may be physically far away, causing a placement problem.
		A FWFT FIFO presents the data on the outputs as soon as it's available, so a deasserted "empty" flag means that the data on the outputs is valid.
		Note that it does not improve timing: The FIFO's dout is passed through, and the FIFO's rd_en depends on the one coming from the application, so its timing is slightly worse than a the bare FIFO it uses.
	www.billauer.co.il /reg_fifo.html (1765 words)

	FIFO queuing disciple
		In FIFO queuing, all packets are treated equally by placing them into a single queue, and then servicing them in the same order that they were placed into the queue.
		The behavior of a FIFO queue is very predictable---packets are not reordered and the maximum delay is determined by the maximum depth of the queue.
		A single FIFO queue impacts all flows equally, because the mean queuing delay for all flows increases as congestion increases.
	www.opalsoft.net /qos/DS-22.htm (586 words)

	What first-in first-out (FIFO) solutions does Altera offer for FLEX 10K® (non-E) devices? (Site not responding. Last check: 2007-11-01)
		A first-in first-out (FIFO) buffer is used to buffer data transferred from one subsystem to another in a design.
		These FIFO buffers are referred to as "asynchronous," "two-clock," or "bisynchronous." The asynchronous LE-based FIFO buffer uses a bank of registers to store data.
		The FIFO buffers are parameterizable, which makes it easy to set the parameters for your system requirements and customize the function for your design.
	www.altera.com /support/kdb/solutions/rd04211998_9240.html (942 words)

	Definition of FIFO
		In a FIFO system, the first items entered are the first ones to be removed.
		Therefore, using the FIFO method, the candy bars are dispensed in the order they were placed in the machine.
		The opposite of FIFO is LIFO, in which the last data entered is the first to be removed.
	www.sharpened.net /glossary/definition.php?fifo (162 words)

	man: fifo
		As the channels generated by fifo grow as necessary they are always writable.
		One possible application of memory channels created by memchan or fifo is as temporay storage device to collect data coming in over a pipe or a socket.
		If part of the processing of the incoming data is to read and process header bytes or similar fifo are easier to use as they do not require seeking back and forth to switch between the assimilation of headers at the beginning and writing new data at the end.
	www.hmug.org /man/n/fifo.php (348 words)

	POSIX FIFO and Shared Memory - fsmlabs.com (Site not responding. Last check: 2007-11-01)
		Creating and using a real-time FIFO is no different than doing the same under a UNIX system.
		The mkfifo() call must allocate space for the FIFO and other record-keeping structures which cannot be done in a real-time context.
		Turning this option on does allocate space at run-time that may be unused so it is best to limit the number of allocated FIFOs to what you know you will use or avoid the need for pre-allocated FIFOs entirely.
	www.fsmlabs.com /posix-fifo-and-shared-memory-2.html (254 words)

	First in First Out Queue by Valvano
		Without the FIFO we would have to produce 1 piece of data, then process it, produce another piece of data, then process it.
		A FIFO is also used when you ask the computer to print a file.
		The advantage of the FIFO is it allows you to continue to use your computer while the printing occurs in the background.
	users.ece.utexas.edu /~valvano/assmbly/fifo.htm (754 words)

	fifo - Definitions from Dictionary.com
		FIFO may be used by a individual or a corporation.
		For taxation purposes, FIFO assumes that the assets that are remaining in inventory are matched to the assets that are most recently purchased or produced.
		Because of this assumption, there are a number of tax minimization strategies associated with using the FIFO asset-management and valuation method.
	dictionary.reference.com /browse/fifo (282 words)

	Programmable Logic DesignLine \| Building an FPGA FIFO without using logic resources
		For FIFOs utilizing one RAM block, programmable aspect ratios of 256x18 or 512x9 are independently configurable on the input and output ports.
		For FIFOs utilizing two RAM blocks, programmable aspect ratios of 256x36, 512x18, or 1024x9 are independently configurable on the input and output ports.
		Now consider a slightly more complex scenario where the FIFO is also required to output almost empty/full flags and/or output vectors indicating the number of elements that are present in the FIFO.
	www.pldesignline.com /howto/showArticle.jhtml;jsessionid=JMDEPNN5QLVMKQSNDBESKHA?articleID=173500175 (1677 words)

	D16550 Soft Configurable UART with FIFO
		In FIFO mode internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit directions.
		The core is perfect for applications, where the UART Core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip, as well as for standalone implementation, where several UARTs are required to be implemented inside a single chip, and driven by some off-chip devices.
		The Rx FIFO is 16 levels (16550) or 64 levels (16750) deep, it receives data until the number of bytes in the FIFO equals the selected interrupt trigger level.
	www.hitechglobal.com /ipcores/D16550.htm (1170 words)

	Sync + FIFO
		The first articles I would probably give mark from poor to excellent but they was all what I refer as "university articles", the last one probably would get a C grade in the university but it got A from me as Eng.
		And again FIFO while have its own complication is not something that should be put aside or consider as "fl magic" like EMI.
		Now if you want to do analog circuit design of full-custom ASIC flip-flops to tweak the the metastability window a few picoseconds smaller at the same statistical certainty level, I'll agree that that may no longer be a basic skill.
	www.codecomments.com /VHDL/message473992-4.html (1678 words)

	D16750: Configurable UART with FIFO
		In FIFO mode internal FIFOs are activated allowing 64 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit directions.
		In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow through the RTS output and the CTS input signals.
		In the FIFO mode transmitter and receiver are each buffered with 16 byte or 64 byte FIFO to reduce the number of interrupts presented to the CPU
	www.latticesemi.com /products/intellectualproperty/dcdcores/d16750configurableuartwit.cfm (584 words)

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