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Topic: Formal verification

Related Topics

Program verification

Formal logic

Program specification

Formal system

Static code analysis

Model checking

VDM specification language

Hoare logic

Vienna Development Method

Z specification language

Design by contract

Software testing

Installation testing

B specification language

Usability testing

	CFV'07 --- Workshop on Constraints in Formal Verification 2007
		Formal verification is of crucial significance in the development of hardware and software systems.
		The main goals of the Constraints in Formal Verification workshop are to bring together researchers from the CSP/SAT and the formal verification communities, to describe new applications of constraint technology to formal verification, to disseminate new challenging problem instances, and to propose new dedicated algorithms for hard formal verification problems.
		This workshop will be of interest to researchers from both academia and industry, working on constraints or on formal verification and interested in the application of constraints to formal verification.
	www.miroslav-velev.com /cfv07.html (495 words)

	Formal verification - Wikipedia, the free encyclopedia
		In the context of hardware and software systems, formal verification is the act of proving or disproving the correctness of a system with respect to a certain formal specification or property, using formal methods of mathematics.
		Formal verification can be used for example for systems such as cryptographic protocols, combinatorial circuits, digital circuits with internal memory, and software expressed as source code.
		The verification of these systems is done by providing a formal proof on an abstract mathematical model of the system, the correspondence between the mathematical model and the nature of the system being otherwise known by construction.
	en.wikipedia.org /wiki/Formal_verification (621 words)

	Formal Verification (Site not responding. Last check: )
		Then proceed with the verification process by first determining what needs to be added in the way of conditions to show loop consistency, and then by demonstrating that these are valid conditions, to be substituted for the loop assertion.
		A verification condition is formed by stating, as the premise of the theorem, the initial assertion that is true on entry to the program.
		One verification condition is written for the true side of the decision and one verification condition is written for the false side of the decision.
	www.ee.cooper.edu /courses/course_pages/past_courses/EE352/FV1.html (4100 words)

	Chapter 4 Web book - Formal Verification
		Formal specification is a specification expressed in a language whose vocabulary, syntax, and semantics are formally defined, and which has a mathematical basis.
		Formal verification is the process of determining whether or not the products of a given phase in the life-cycle fulfill a set of established requirements, using a formal mathematical notation.
		After-the-fact verification, after the system is built with a standard method, a formal specification is derived and formal verification of the implementation may be done.
	www.cis.ksu.edu /~hankley/d841/Fa99/chap4.html (3976 words)

	NCSC-TG-014-89 - Guidelines for Formal Verification Systems
		Verification systems placed on the ETL will either be significant improvements to systems already on the list or will provide a useful approach or capability that the currently endorsed systems lack.
		Formal Verification The process of using formal proofs to demonstrate the consistency (design verification) between a formal specification of a system and a formal security policy model or (implementation verification) between the formal specification and its program implementation.
		Theory A formal theory is a coherent group of general propositions used as principles of explanation for a particular class of phenomena.
	www.fas.org /irp/nsa/rainbow/tg014.htm (7604 words)

	Formal verification made easy
		Formal verification (FV) is considered by many to be complicated and to require considerable mathematical knowledge for successful application.
		Verification: Since the control logic is the major source of design errors, verification models containing only the control logic are the most important models.
		The first column shows the switch simulation, the formal verification of the command transfer process, and the extrapolation of FV to the complete switch.
	www.research.ibm.com /journal/rd/414/schlipf.html (3721 words)

	EDN Access--01.01.98 Chip verification: a formal affair? (Site not responding. Last check: )
		Simply put, formal verification is a means of applying rigorous mathematical methods to exhaustively verify a system's operation.
		Another advantage of formal verification is that it is exhaustive--the tool verifies a design under all possible conditions.
		Formal verification is not a substitute for but a complement to vector-based simulation methods.
	www.edn.com /archives/1998/010198/01df_02.htm (2592 words)

	The Formal Verification of the Fairisle ATM Network
		Whilst demonstrating that formal verification can detect errors and give an indication of their locations, this also highlights a reason for integrating formal methods into the design process rather than tagging it on as an afterthought.
		Formal proof is a good way of finding small numbers of obscure errors, but it is better if more obvious errors are found by other methods prior to the proof attempt.
		We describe the formal verification of an implementation of the switching element of the Fairisle ATM switch.
	www.dcs.qmw.ac.uk /~pc/research/atmproof/atmproof.htm (6037 words)

	EETimes.com - 'Deep' formal verification powers assertions
		In this article, we discuss these technologies in the context of assertion-based verification, which has proven to be an effective way of applying formal verification in a mainstream ASIC design flow.
		Basically, the objective of formal technology in ABV is first, to minimize the number of indeterminate assertions, and second, to provide feedback to the user about how thoroughly each indeterminate assertion has been verified.
		Static formal verification (SFV) uses a variety of algorithms to prove that it is impossible to violate an assertion, starting from the reset state of the DUT, without violating the constraints.
	www.eetimes.com /news/design/showArticle.jhtml?articleID=16504695 (2571 words)

	EETimes.com - Formal verification: where to use it and why (Site not responding. Last check: )
		Today, formal verification can be more valuable applied partially within blocks by choosing the functions that have the highest return.
		There are three objectives for use of formal tools: first, to accomplish what conventional methods cannot, such as proving that a particular property is always true; second, to achieve what other methods can do, but significantly faster; and, lastly, to enhance current tools and methods by providing another approach to achieve full coverage.
		The benefit of formal verification is greatest if we can fix all the block-level functional bugs prior to system-level verification, where bug-fixes are more time-consuming.
	www.eetimes.com /news/design/showArticle.jhtml;jsessionid=ET0UL31NVUGACQSNDLPCKHSCJUNN2JVN?articleID=190301228 (942 words)

	Formal Verification of Pipelined Microprocessors
		This formal verification should be done such that any third party is able to verify the correctness with low effort, i.e., we aim to provide a proof of correctness that can be checked mechanically.
		There are many publications on the formal verification of sequential machines, e.g., Cohn verified the VIPER processor [Coh87], Joyce verified the Tamarack [Joy88a, Joy88b], Hunt verified the FM8501 [Hun94], and Windley verified the AVM-1 [Win95].
		The formal verification of a pipelined processor is reported in [BS89]: Bickford and Srivas verify a three stage DLX-like RISC processor.
	www.kroening.com /diss/intro.html (1727 words)

	Formal Verification (Site not responding. Last check: )
		The goal of this research is to introduce new techniques in building decompositions of systems from high-level descriptions of designs into abstract representations which are complete with respect to a property of interest.
		We have recently developed a novel approach for formally verifying both safety and liveness properties of designs using sequential ATPG tools.
		The mapping of the properties to the monitor circuit is described in detail and the process is shown to be sound and complete.
	www.cerc.utexas.edu /~jaa/verif/formal.html (367 words)

	Formal verification of state machine models \| Formal verification
		visualSTATE incorporates verification of the designed state machines, based on formal verification theories with their roots in low-level hardware design, like integrated circuits etc. This is a brief introduction to the concept of formal verification that shows why you can trust the verification results.
		The visualSTATE verification is an example of model checking, which is a set of different methods of algorithmically verifying that a model satisfies a specification.
		Since the ROBDD encoding is a formal and complete representation of a (finite) state machine system and each property can be expressed as operations on the decision diagrams, it is guaranteed that the verification process can verify each property.
	www.iar.com /p147593/p147593_eng.php (1253 words)

	Research overview -- Formal verification and formal methods
		Murphi is a description language and automatic formal verification system for the high-level description of finite-state systems, including many protocols and distributed algorithms.
		We have formally specified and verified the core subset of the PCI bus protocol.
		We have been formally verifying high-level processor descriptions using a symbolic simulator and a decision procedure for a quantifier-free fragment of first-order logic with equality and uninterpreted functions.
	verify.stanford.edu /dill/research.html (514 words)

	Mentor Graphics 0-In Formal Verification
		This is the main reason that designers complement their simulation-based verification methodology with formal verification.
		The 0-In® Formal verification solution offers the highest capacity and performance available along with a set of formal verification engines to help you find your most complex bugs.
		Formal verification experts can prove the most complex properties and find the most complex bugs.
	www.mentor.com /products/fv/abv/0-in_fv/index.cfm (288 words)

	Introduction to Formal Verification of Hardware and Protocols
		After taking this course, a student should be able to understand the basic concepts and techniques of computer-aided formal methods, know what such techniques are and are not good for, and have a sense of which techniques and tools might be most useful when faced with a real-world verification problem.
		Ching-Tsun Chou is a Platform Architect and Verification Engineer at Intel Corporation, where he applies formal methods to the design, definition, and verification of complex protocols used in distributed shared memory systems.
		Earlier he was a Verification Engineer in Intel’s Itanium™ processor design team, where worked on both formal and simulation-based hardware verification, and a VLSI CAD Researcher in Fujitsu Labs of America, where he worked on the application of synchronous programming languages to hardware design.
	home.pacbell.net /ctchou/scu-cafm.html (1329 words)

	Formal Verification of Reactive Systems (Site not responding. Last check: )
		Under the term formal verification we comprise the techniques used to reason formally about the behavior of digital systems.
		In a general way, the verification problem may be stated as follows: Given a specification of the behavior of a system and an implementation, verify formally that the implementation satisfies the specification.
		Formal verification specifically tries to avoid this kind of error by guaranteeing that the final product is "correct".
	vlsi.colorado.edu /~abel/pubs/verification.html (319 words)

	Introduction to Formal Verification
		Formal verification is the process of checking whether a design satisfies some requirements (properties).
		We are concerned with the formal verification of designs that may be specified hierarchically (as illustrated in the previous section); this is also consistent with how a human designer operates.
		In order to formally verify a design, it must first be converted into a simpler ``verifiable'' format.
	vlsi.colorado.edu /~vis/doc/VisUser/vis_user/node4.html (2229 words)

	hvg concordia: researchs:Verification of FP Hardware
		We formally analyse the protocol, with a special focus the processes Byzantine behaviour, using an adaptive combination of techniques including Model Checking, Theorem Proving and Analytical mathematics.
		Layouni, J. Hooman and S. Tahar: Formal Specification and Verification of the Intrusion-Tolerant Enclaves Protocol; Technical Report, Concordia University, Department of Electrical and Computer Engineering, November 2003.
		Layouni, J. Hooman, and S. Tahar: Modeling and Verification of Leaders Agreement in the Intrusion-Tolerant Enclaves Using PVS; Technical Report, Concordia University, Department of Electrical and Computer Engineering, May 2003.
	hvg.ece.concordia.ca /Research/APPL/CRYPTO/CRYPTO.html (306 words)

	Xavier Leroy - Home page
		[11/2007] Publication: Formal verification of translation validators: A case study on instruction scheduling optimizations, with Jean-Baptiste Tristan, POPL 2008.
		[07/2007] Publication: Mechanized verification of CPS transformations, with Zaynah Dargaye, LPAR 2007.
		[08/2006] Publication: Formal verification of a C compiler front-end, with Sandrine Blazy and Zaynah Dargaye.
	pauillac.inria.fr /~xleroy (347 words)

	Formal verification \| www.liberouter.org
		Formal verification is state-of-the-art domain of applied computer science.
		In our Formal verification team we formalize the specification of components under verification using modal and temporal logics.
		Clicking on darkned boxes the verification results for a particular unit can be seen in the form of Verification report.
	www.liberouter.org /formal_verification/index.php (160 words)

	Formal Verification of Hardware Designs
		Apply a property-dependant reduction to each parallel component of a distributed system in order to traverse a smaller state space during the model-checking verification.
		Formalize an incremental design approach and the transformations of properties along the design process in order to automate some non-regression verifications.
		Verification of safety and liveness properties with VIS.
	www-asim.lip6.fr /recherche/formal (176 words)

	Spin - Formal Verification
		Three examples of inspiring applications of Spin in the last few years include the verification of the control algorithms for the new flood control barrier built in the late nineties near Rotterdam in the Netherlands.
		The verification work was carried out by the Dutch firm CMG (Computer Management Group) in collaboration with the Formal Methods group at the University of Twente.
		Later, at JPL a separate verification of the software used on this mission was also done (pdf).
	spinroot.com /spin/whatispin.html (2258 words)

	Formal Methods and Dependable Systems
		Systematic Formal Verification for Fault-Tolerant Time-Triggered Algorithms (1999) (1999)
		Systematic Formal Verification for Fault-Tolerant Time-Triggered Algorithms (1997) (1997)
		Formal Verification of an Interactive Consistency Algorithm for the Draper FTP Architecture Under a Hybrid Fault Model (1994)
	www.csl.sri.com /sri-csl-fm.html (254 words)

	Formal Verification Surveys
		D. Dill, "Formal Verification: Experiences and Future Prospects", slides from a presentation at POPL 1999.
		D. Dill, "Alternative Approaches to Formal Verification (Symbolic Simulation)", slides from a presentation at CAV 1999.
		Various Contributors, "Survey of Formal Verification", IEEE Spectrum, June 1996, pp.
	www.cerc.utexas.edu /~jay/fv_surveys (458 words)

	251-0247-00 Formal Verification (Site not responding. Last check: )
		This effect is even more problematic in the light of shorter innovation cycles and the increasing pressure to react quickly to the market.
		One solution, if not the only alternative in the long run, is to consequently use automated formal methods.
		There are no special requisites for this lecture, except that we expect some interest in formal approaches and algorithms.
	www.inf.ethz.ch /personal/daniekro/classes/251-0247-00/ws2005-2006 (246 words)

	Formal Verification Moves Into Design Phase
		Traditionally, formal verification is used after the fact for bug hunting or design-rule checking.
		Users apply the tool early in the RTL coding process before the blocks are submitted to verification teams for system simulation (see the figure).
		Typically, formal tools are applied to implementation-specific assertions that relate to relatively small portions of the RTL.
	www.elecdesign.com /Articles/Index.cfm?ArticleID=8006 (746 words)

	Real Intent Introduces Performance Breakthrough in Formal Verification
		SUNNYVALE, Calif. --December 12, 2005- Real Intent, a leading supplier of formal verification software used to improve verification efficiency for semiconductor designs, today announced that its Verix 5.0 software release with a new breakthrough Convergence Engine is now shipping in volume.
		Verix products utilize the power of formal analysis to verify design assertions and either prove them correct or detect bugs that are hard to find.
		The Verix family includes Expressed Intent Verification (formal assertion based verification), Clock Intent Verification (metastability and hazard detection) and Implied Intent Verification (automatic design verification).
	www.realintent.com /news/pr-2005/PR-DEC-12-05.html (900 words)

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