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Topic: Futurebus

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	Futurebus -- Facts, Info, and Encyclopedia article (Site not responding. Last check: 2007-10-17)
		Futurebus looked to fix these problems and create a successor to systems like VMEbus with a system that could grow in speed without effecting existing devices.
		In the case of Futurebus this was reversed, the whole system was being designed as during the standardization effort.
		One member did a quick back-of-the-envelope calculation and showed that by the time Futurebus+ shipped, it would already be too slow for the (A mainframe computer that is one of the most powerful available at a given time) supercomputer market.
	www.absoluteastronomy.com /encyclopedia/f/fu/futurebus.htm (671 words)

	Interface between buses attached with cached modules providing address space mapped cache coherent memory access with ...
		Futurebus arbitration and control circuit 40 checks control signals on Futurebus 12 to determine if a write operation is intended (step 126), and if so, circuit 40 turns on enable signal EN7 (step 128), causing buffer 36 to connect the Futurebus address/data lines to local data bus 14.
		Futurebus arbitration and control circuit 40 places the SNOOP signal on Futurebus 12 and responds appropriately in response to retry requests from cache masters on the Futurebus.
		Control data transmitted by the Futurebus master during the Futurebus data cycle indicates the length and byte position of words to be accessed, and in response, Futurebus arbitration and control circuit 40 transmits the LANE data conveying this information to circuit 304 of FIG.
	www.freepatentsonline.com /5072369.html (6368 words)

	Futurebus+ (Site not responding. Last check: 2007-10-17)
		The internal operation of the Futurebus+ standard is explored, as well as the addressing, arbitration and data transfer is implemented within the bus architecture is investigated.
		The Futurebus+ specification is one of the most technically complex bus standards ever produced.
		Futurebus is for the most part a dead bus.
	granite.sru.edu /~stringer/fb.html (1838 words)

	Futurebus interrupt subsystem apparatus - Patent 5060139
		The backplane signal lines of the Futurebus 28 comprise a number of functional buses including an address/data bus 29, a control acquisition or arbitration bus 30, and a utility bus 31, which includes power leads and geographical address lines that identify each of the physical slots on the backplane into which modules are connected.
		Devices requiring Futurebus 28 access generate, in the control logic 50, a signal, ac, on line 56, which is applied to the driver of the bus transceivers 42 corresponding with the AC* signal line 52.
		In order to transmit interrupts across the Futurebus, the interrupt sources from the VMEbus 20 and also those generated on the interface board 36 are mapped and converted into message numbers higher than the arbitration numbers utilized by devices on the arbitration bus 30 contending for use of the data/address bus 29.
	www.freepatentsonline.com /5060139.html (5796 words)

	[No title] (Site not responding. Last check: 2007-10-17)
		At the time of our investigation, however, the Futurebus+ specification was in development by the IEEE and a wide range of interest was evident throughout the industry.
		Compliance with the Futurebus+ specifications influenced most mechanical aspects of the module compartment design, as is evident from the centerplane, card cage, module construction and size, and power supply voltage specifications and implementations.
		Therefore the Futurebus+ bridge and local I/O control logic were implemented in programmable logic to isolate the high risk design areas from the ASIC development process.
	www.research.compaq.com /wrl/DECarchives/DTJ/DTJ805/DTJ805SC.TXT (8831 words)

	Futurebus Reborn? \| COTS Journal (Site not responding. Last check: 2007-10-17)
		Just like the Futurebus effort did in the 80s, the current committees are trying to gather support by extending/expanding/reducing (whatever it takes) the proposed specification.
		And to you Futurebus wannabes—you may be able to create a document that describes a new bus architecture (with let’s say a separate “profile” for each of you) that fits your needs, allowing you to control who may supply products into your systems.
		During the Futurebus heyday when I was head of a board company I asked a senior marketing manager from DEC how my company could participate in providing product to DEC for inclusion in their systems.
	www.cotsjournalonline.com /home/article.php?id=100123 (925 words)

	IEEE Standards Description: 10857-1994
		Transmission of data over the mulitplexed address/data highway is governed by one of two intercompatible transmission methods: a) a technology-independent, compelled-protocol, supporting broadcast, broadcall, and transfer intervention (the minimum requirement for all Futurebus+ systems), and b) a configurable transfer-rate, source-synchronized protocol supporting only block transfers and source-synchronized broadcast for systems requiring the highest possible performance.
		Futurebus+ takes its name from its goal of being capable of the highest possible transfer rate consistent with the technology available at the time modules are designed, while ensuring compatibility with all modules designed to this standard both before and after.
		It is intended that this Internation Standard be used as a key component of an approved IEEE Futurebus+ profile.
	standards.ieee.org /reading/ieee/std_public/description/busarch/10857-1994_desc.html (311 words)

	Futurebus Description, Pinout, Signal Name, and Manufacture links. Futurebus+
		Futurebus and then Futurebus+ is a back-plane bus specification which defines both the Physical and Electrical layers.
		The Futurebus bus width started at 32 bits wide, but now with Futherbus+ the width may be up to 256 bits.
		FutureBus connectors, which use 2mm style have a mating distance of 10mm.
	www.interfacebus.com /Design_Connector_Futurebus.html (915 words)

	Evaluation of a FutureBusplus Processor module (Site not responding. Last check: 2007-10-17)
		The IEEE Standard 896, better known under the name of Futurebus+ Standard, provides the comprehensive specifications for a high performance bus architecture where speed and functionality are the most important components.
		Futurebus+ is not one monolithical bus standard, but rather an overall architectural standard made up of many parts.
		Futurebus+ transactions across the bus are automatically generated when a processor off-board memory address is specified for reading or writing.
	kwibus.home.cern.ch /kwibus/career/Fbplus/Fbp_eva.html (4466 words)

	Microprocessor Report : Futurebus+ coming of age: high bandwidth and advanced features are key attractions. (part one ... (Site not responding. Last check: 2007-10-17)
		Start / M / Microprocessor Report / May 27, 1992 / Futurebus+ coming of age: high bandwidth and advanced features are key attractions.
		Futurebus+ coming of age: high bandwidth and advanced features are key attractions.
		John was the architect of the Futurebus and Futurebus+ parallel protocols, central arbitration, and Profile F He is the chairman of P896.8, which is working to develop a next-generation desktop/mezzanine bus.
	static.highbeam.com /m/microprocessorreport/may271992/futurebuscomingofagehighbandwidthandadvancedfeatur/index.html (248 words)

	Flexible Futurebus connector system: News from Harwin
		Harwin's new futurebus connector system is a modular 2.00mm grid system for high density, high-speed signal board-to-backplane applications for datarates of 0.622Gbit/s.
		The connectors were developed in a joint strategic alliance with Starconn, and are designed for use in telecomms, networking and high-end computing applications.
		The Futurebus system offers design flexibility with PCB receptacles and headers that are end to end stackable.
	www.electronicstalk.com /news/haa/haa110.html (219 words)

	SCI Industrial Takeup and Future Developments (Site not responding. Last check: 2007-10-17)
		Multiprocessing support in Futurebus evolved to include fair and prioritized arbitration; a set of primitives to handle process synchronization, locks and mutual exclusion; reflective memory, then cache coherence; and a variety of maintenance features as required for large systems.
		Therefore, the Futurebus+ group was formed and began to revise the 1987 spec, to add more priority levels and more performance options and packaging options.
		Futurebus+ was difficult partly because there was complete freedom how to do everything, so it was hard to agree which of several methods should be used.
	www.scizzl.com /Perspectives.html (6500 words)

	Futurebus - TheBestLinks.com - IEEE 896, CPU, Computer bus, Memory, ... (Site not responding. Last check: 2007-10-17)
		Futurebus - TheBestLinks.com - IEEE 896, CPU, Computer bus, Memory,...
		IEEE 896, Futurebus, CPU, Computer bus, Memory, PCI, RAM, Seawolf class...
		You can add this article to your own "watchlist" and receive e-mail notification about all changes in this page.
	www.thebestlinks.com /IEEE_896.html (777 words)

	Futurebus - a reference guide from Electronicstalk
		We see from your search that you're looking for information on the term "Futurebus", and we have a large number of manufacturers' news stories and technical articles here on Electronicstalk which will be of interest.
		Start with the news story Futurebus data connectors from Genalog, which we summarised at the time by saying "The Harwin Futurebus connector system is based on a modular 2mm grid for high-density high-speed signal board-to-backplane applications at a datarate of 0.622Gbit/s.".
		In July 2002, we covered the news from Harwin concerning its Futurebus connector system - take a look at Flexible Futurebus connector system which says: "Harwin's new Futurebus connector system is a modular 2.00mm grid system for high density, high-speed signal board-to-backplane applications for datarates of 0.622Gbit/s.".
	www.electronicstalk.com /guides/futurebus.html (223 words)

	"Simplifying FutureBus Backplane Impedance Predictions and Simulating FutureBus Performance"
		The accurate prediction of backplane impedance values is an important step in the design, simulation and performance evaluation of backplanes for high performance digital systems.
		For example, specific knowledge of the impedance and propagation delay in FutureBus based designs for various conditions of loading of the backplane bus is critical to the prediction of timing relationships as well as the achievement of the "clean" incident wave switching required by FutureBus device designs.
		This paper provides the theoretical justification for the application of the backplane capacitive loading formulas in determining impedance and propagation delay and illustrates their use with a design case study.
	www.nesa.com /fbus.html (243 words)

	Citations: IEEE Standard for Futurebus+ --- Logical Protocol Specification - Std (ResearchIndex) (Site not responding. Last check: 2007-10-17)
		For SCI systems, depending on the implementation, the bandwidth can be 1 Gbyte second (GaAs chips and special cable up to 10 meters) or 1 Gbit second (CMOS chips and fiber optical cables) The communication latency between two nodes is in the range of sub microsecond to tens of microseconds....
		This inclusion is easily accomplished and, in addition, it allows the system designer to concentrate on the application level model and assume the construction of the bus level model to be already concluded.
		and 896.2 [7] An easy to read introduction to the Futurebus can be found in [10] A bus level model with multiple priorities and classes was investigated by Takine et al.
	citeseer.ist.psu.edu /context/367962/0 (1048 words)

	Futurebus data connectors: News from Genalog
		The Harwin Futurebus connector system is based on a modular 2mm grid for high-density high-speed signal board-to-backplane applications at a datarate of 0.622Gbit/s.
		Designed for use in telecomms, networking and high-end computing applications, the Harwin futurebus connector system is based on a modular 2mm grid for high-density high-speed signal board-to-backplane applications at a datarate of 0.622Gbit/s.
		End-to-end stackable PCB receptacles and headers provide design flexibility.
	www.electronicstalk.com /news/geb/geb124.html (205 words)

	A Futurebus Interface from Off-the-Shelf Parts (Site not responding. Last check: 2007-10-17)
		A Futurebus interface design using standard parts as part of the GRIP (Graph Reduction in Parallel) project is described.
		The GRIP system and the IEEE P896 Futurebus standard are examined.
		Some lessons for designers using Futurebus are drawn from the experience.
	csdl2.computer.org /persagen/DLAbsToc.jsp?resourcePath=/dl/mags/mi/&toc=comp/mags/mi/1991/01/m1toc.xml&DOI=10.1109/40.67745 (308 words)

	Search Results: IEEE Standards Status Report
		The purpose of this handbook is to provide a reference to many of the concepts, rules, and guidelines that are necessary to understand and to follow so that interoperability of Futurebus+ systems and modules is ensured.
		Futurebus+ standards provide systems developers a set of tools with which high-performance bus-based systems may be developed.
		Abstract: Futurebus+ standards provide systems developers with a set of tools with which high performance bus-based systems may be developed.
	standards.ieee.org /cgi-bin/status?896.3-1993 (1111 words)

	National P/N DS3885 - BTL Arbitration Transceiver - MIL-STD-883 [Discontinued] (Site not responding. Last check: 2007-10-17)
		The DS3885 is one in a series of transceivers designed specifically for the implementation of high performance Futurebus+ and proprietary bus interfaces.
		The DS3885 Arbitration Transceiver is designed to conform to IEEE 1194.1 (Backplane Transceiver Logic-BTL) as specified in the IEEE 896.2 Futurebus+ specification.
		The Arbitration Transceiver incorporates the competition logic internally which simplifies the implementation of a Futurebus+ application by minimizing the on board logic required.
	www.national.com /pf/DS/DS3885.html (1174 words)

	Citations: Using Futurebus in a Fifth Generation Computer - SL (ResearchIndex) (Site not responding. Last check: 2007-10-17)
		Peyton Jones SL, "Using Futurebus in a Fifth Generation Computer", Microprocessors and Microsystems 10(2), (March 1986), pp.
		PE3 local bus FUTUREBUS Figure 1: A GRIP board GRIP consists of up to 20 printed circuit boards, each of which comprises up to four processors, one Intelligent Memory Unit (IMU) JCSH87] and a communication subsystem (see Figure 1) The boards are interconnected using a fast packet switched bus
		Peyton Jones SL, "Using Futurebus in a fifth generation computer", Microprocessors and Microsystems, March 1986.
	citeseer.lcs.mit.edu /context/99039/0 (685 words)

	National P/N DS3875 - FutureBus Plus Arbitration Controller - MIL-STD-883 [Discontinued] (Site not responding. Last check: 2007-10-17)
		The DS3875 Futurebus+ Arbitration Controller is a member of National Semiconductor's Futurebus+ chip set designed specifically for the IEEE 896.1 Futurebus+ standard.
		Additional transceivers included in the Futurebus+ chip set are the DS3883A BTL 9-bit Data Transceiver and the DS3886A BTL 9-bit Latching Data Transceiver.
		The Protocol Controller handles all the handshaking signals between the Futurebus+ and the local bus interfaces, and incorporates a DMA Controller with built-in FIFOs for fast queueing.
	www.national.com /pf/DS/DS3875.html (505 words)

	Business Wire : Oupiin America's Production Time Beats Competition in Futurebus+ Market. @ HighBeam Research (Site not responding. Last check: 2007-10-17)
		Oupiin America, Inc. announces that average production time for their products, specifically the 9111 Series, is only 10 weeks (quicker delivery is available, though air freight charges apply).
		According to sources in the field, our (1)competitors have been unable to deliver Futurebus+ products in a timely manner, due to the fact that some have already reached full production capacity, while others aren't far behind.
		Therefore, their delivery time for such products is averaging 20-30 weeks, with some deliveries stretching out to as long as 32-54 weeks.
	static.elibrary.com /b/businesswire/july262000/oupiinamericasproductiontimebeatscompetitioninfutu/index.html (206 words)

	MSC Project Status Report
		Errata, correction and clarification of IEEE 896.1-1991 Futurebus+ logical layer
		Futurebus+ -- physical layer and profile specifications: errata, corrections, and clarifications
		Standard for Futurebus+ profile M (military): errata, corrections, and clarifications
	grouper.ieee.org /groups/msc/StatusProjects.html (343 words)

	Verification of the Futurebus+ Cache Coherence Protocol - Clarke, Grumberg, Hiraishi, Jha, Long, McMillan, Ness ... (Site not responding. Last check: 2007-10-17)
		Verification of the Futurebus+ Cache Coherence Protocol (1992)
		Abstract: We used a hardware description language to construct a formal model of the cache coherence protocol described in the draft IEEE Futurebus+ standard.
		The result of our project is a concise, comprehensible and unambiguous model of the protocol that should be useful both to the Futurebus+ Working Group members, who are responsible for the protocol, and to actual designers of Futurebus+ boards.
	citeseer.ist.psu.edu /149505.html (533 words)

	Semiconductors Parts begin by FB Page1
		Description: 3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
		Description: 9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver with 30 W termination
		Description: 3.3 V BTL 8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver
	www.abcsemiconductors.com /composants/parts/fb/parts_fb.php (47 words)

	Datasheet catalog for electronic components integrated circuit, transistor, diode, triac, and other semiconductors.
		Datasheet catalog for electronic components integrated circuit, transistor, diode, triac, and other semiconductors.
		9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver with 30 Ohm termination
		9-bit BTL 3.3V latched/registered/pass-thru Futurebus transceiver with 30W termination
	www.datasheetcatalog.com /catalog/p115160.shtml (57 words)

	Molex - 2.00mm (.079) Pitch Milli-Z Electrically Characterized Carrier Systems and Backplane Shroud - 1, 4, 5 and 6 Row ...
		1, 4, 5 and 6 Row Ganged Carriers for HDM, Futurebus*, Metral and Z-Pac Connectors
		Milli-Z carriers are designed to combine Molex 2 to 5 position Milli-Z socket connectors
		4 row end stackable Futurebus carriers are available in 24 and 30 positions
	www.molex.com /product/harness/milliz14.html (252 words)

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