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| | EETimes.com - IC makers gird for 65-nm fray (Site not responding. Last check: 2007-11-06) |
 | | Because the 65-nm node has no major material shifts, few expect similar problems in manufacturing chips with 65-nm line widths. |
 | | Strained silicon, with its gigapascal levels of stress brought to bear on the silicon channel, could cause yield-killing defects, "especially for companies that are new to strained silicon at the 65-nm node," said Scott Thompson, an associate professor at the University of Florida at Gainesville, who helped develop Intel Corp.'s strained technology. |
 | | Franck Arnaud, a CMOS technology development manager at STMicroelectronics, said, "The key change for us at the 65-nm node was not the transistor itself, but the link with design." For example, chips must be laid out in more yield-friendly vertical and horizontal patterns. |
| www.eetimes.com /showArticle.jhtml?articleID=175400161 (742 words) |
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