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| | Performance Counters Library - hardware registers |
 | | This example introduces hardware registers pmc_uint32_t pmc_uint64_t Control Registers -- CR0, CR4, EFLAGS Model-Specific Registers -- TSC, PMC control, PMC counters Model-specific semantics pmc_query, pmc_test, pmc_test.c pmc_enable, pmc_disable, pmc_able.c These are implementation details and various opinions that can be skipped by most readers. |
 | | The control registers CR0, CR1, CR2, CR3, CR4 and EFLAGS are described in the Intel Architecture publications. |
 | | That is, they are first and foremost not strictly part of the Intel Architecture, and their implementations and semantics have changed from one Pentium model to the next. |
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